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Order Information

Standard temperature range -40

PCI5IP

http://www.dyneng.com/pci5ip.html

Full length PCI card with 5 IP positions

-STB

Add Strobe Header

-CC

Add conformal coating

-ROHS

Add ROHS processing and label.

-EJ

Add latch block release/retention mechanism
to ribbon cable connectors. Please note this
option is slightly out of spec for PCI height.

-BB

Switch to blank bezel. Standard is cable
egress friendly with cutout. Changes position
A IO connector from right angle through the
bezel to vertical.

IP-DEBUG-BUS

http://www.dyneng.com/ipdbgbus.html

IP test points, reset switch, fused power, quick
switch isolated interface lines to allow hot
swapping of IP cards.

IP-DEBUG-IO

http://www.dyneng.com/ipdbgio.html

Isolate the IO connector to help with
debugging. 50-pin header for system cable
connection. 50 testpoints suitable for wire-
wrap to allow loop-back connections.

HDRterm50

http://www.dyneng.com/HDRterm50.html

50-pin header to 50 screw terminal converter
with DIN rail mounting.

HDRcabl50

50 pin ribbon cable compatible with PCI5IP
and HDRterm50. Various lengths off-the-shelf,
and custom

All information provided is Copyright Dynamic Engineering

Содержание PCI5IP

Страница 1: ...odule Carrier Key Features Fast Access with integrated PCI IP Bridge 5 IP Positions with IO 8 32 MHz IP operation 8 16 32 bit accesses supported 16 32 bit IP module support Data Alignment Byte and Wor...

Страница 2: ...Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and can radiate radio frequency energy Op...

Страница 3: ...20 pci5ip_intreg_int 23 pci5ip_intreg_dswitch 25 APPLICATIONS GUIDE 26 Interfacing 26 Engineering Kit 26 IP Module Logic Interface Pin Assignment 27 Construction and Reliability 28 MTBF 28 Thermal Co...

Страница 4: ...MAP 13 FIGURE 5 PCI5IP CONTROL PORT 17 FIGURE 6 PCI5IP SLOT CONTROL PORT 20 FIGURE 7 PCI5IP 16 BIT BYTE SWAPPING 21 FIGURE 8 PCI5IP 32 BIT BYTE SWAPPING 21 FIGURE 9 PCI5IP INTERRUPT STATUS PORT 23 FIG...

Страница 5: ...are 16 bit devices Byte word and long word accesses are supported Bytes can be to any address Word accesses need to be word aligned Long word accesses need to be long word aligned Each of the access t...

Страница 6: ...ster sets defined to operate efficiently with a little endian interface The default settings on the PCI5IP are straight through byte for byte and D15 0 written to address 0x00 before D31 D16 written t...

Страница 7: ...an be switched at any time Hardware insures that the clocks switch basis on a clock period boundary to provide seamless operation PCI5IP supports interrupts from each slot with separate mask bits Two...

Страница 8: ...on mini planes to the FPGA The FPGA is effectively isolated from the IP slots by the regulators and additional filtering PCI5IP is well behaved with low noise power provided to each of the slots PCI5I...

Страница 9: ...vantage of the differential definition just outlined PCI5IP conforms to the VITA standard for IndustryPack Carriers This guarantees compatibility with multiple IndustryPack compatible modules PCI5IP c...

Страница 10: ...Revision G FLASH the PCI Core is now a Dynamic Engineering design This is important because we have corrected a defect in the core previously used which interfered with use in external chassis FLASH...

Страница 11: ...e positions Full ID IO INT and Memory space allocated for each IP 8 or 32 MHz operation in each slot independently byte word long word access 32 bit access to 16 bit slots with static or incrementing...

Страница 12: ...is provided Each of the 5 IP positions can have an IP installed IndustryPack s are installed by pushing the mezzanine card onto the connector pair on the PCI5IP Each position is clearly marked The IO...

Страница 13: ...00 starting address of slot B C IO pci5ip_iode_st 0x00270000 starting address of slot D E IO pci5ip_inta_st 0x00310000 starting addr of slot A INT space pci5ip_intb_st 0x00340000 starting addr of slot...

Страница 14: ...he VendorId 0x10EE and the CardId 0x000B for the PCI5IP Interrupts are requested by the configuration space The VendorId and CardId parameters are used by the OS to identify the card and in some cases...

Страница 15: ...mber is used to further differentiate between multiple cards of the same type The IP module positions are labeled A E in the silk for identification PCI5IP has an integrated PCI interface with IP brid...

Страница 16: ...access With word and byte swapping you can account for the organization of the registers on the IP Some IP s convert 16 bit accesses to double 8 bit accesses IP QuadUART for example If your IP has 16...

Страница 17: ...set is synchronized to the IP clock per the IP interface specification The duration is controlled by the user software 200 mS is a suggested minimum time to enable for resetting purposes In addition t...

Страница 18: ...check the status during operation During initialization if the software is checking to see what is installed or what address range is valid on an IP the status can be polled to see if the IP responde...

Страница 19: ...he Bus Error Status bits in all of the channels to be cleared as well as the state machine that manages the bus error interrupt Remember to reset to 0 for normal operation Usually only needed after en...

Страница 20: ...FIFO is mapped to a single IP address since it allows double IP accesses to the same address with a single PCI transfer All types of access are affected i e MEM IO INT and ID Each slot has independent...

Страница 21: ...Swap feature for big endian little endian conversion 16 bit ports D15 8 D7 0 D31 24 D23 16 FIGURE 7 PCI5IP 16 BIT BYTE SWAPPING 32 bit ports D31 24 D7 0 D23 16 D15 8 D15 8 D23 16 D7 0 D31 24 FIGURE 8...

Страница 22: ...effectively accessed in reverse order For example if the IP registers are organized with the MS data at address 0x00 and the LS data at 0x02 then a single 32 bit write can be made to 0x00 with addres...

Страница 23: ...NOT SET 11 0 10 INTRN 1 SET 0 NOT SET 9 MASKED E1 8 MASKED E0 7 MASKED D1 6 MASKED D0 5 MASKED C1 4 MASKED C0 3 MASKED B1 2 MASKED B0 1 MASKED A1 0 MASKED A0 1 SET 0 NOT SET FIGURE 9 PCI5IP INTERRUPT...

Страница 24: ...e0 pci5ip_int slot _st 0x02 If the IP does not require a Vector fetch to clear the interrupt then proceed with IO or other accesses as necessary The Bus Error status bit is set high when a Bus Error i...

Страница 25: ...the switch figure below indicates a 0x12 The switch can be used for any user purpose or to identify a particular PCI5IP in a system with more than one card installed Dynamic Engineering Driver softwa...

Страница 26: ...supplies from one switch Connecting external voltages to the PCI5IP when it is not powered can damage it as well as the rest of the host system This problem may be avoided by turning all power supplie...

Страница 27: ...D10 A2 14 39 D11 n c 15 40 D12 A3 16 41 D13 INTREG0 17 42 D14 A4 18 43 D15 INTREQ1 19 44 BS0 A5 20 45 BS1 Strobe 21 46 12V A6 22 47 12V Ack 23 48 5V reserved 24 49 GND GND 25 50 NOTE 1 The error signa...

Страница 28: ...ake consistent correct insertion easy and reliable The IP Module can be secured against the carrier with the connectors If more security against vibration is required then IP mounting kit can be used...

Страница 29: ...r charges must accompany the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased direct...

Страница 30: ...or interrupt DMA No DMA Support implemented at this time Onboard Options All Options are Software Programmable Interface 50 pin Header Connectors with differentially routed controlled impedance matche...

Страница 31: ...from right angle through the bezel to vertical IP DEBUG BUS http www dyneng com ipdbgbus html IP test points reset switch fused power quick switch isolated interface lines to allow hot swapping of IP...

Страница 32: ...wiring is 1 1 from the IP IO connector to the PCI5IP header connector The connectors are numbered to match standard ribbon cable as shown in the figure to the right Matched length impedance controlle...

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