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Chapter 3 Hardware Installation
21
Chapter 3
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
CH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
LPC_AD0
B4
LPC_AD1
B5
LPC_AD2
B6
LPC_AD3
B7
LPC_FRAME#
B3
O CMOS
3.3V / 3.3V
LPC frame indicates the start of an LPC cycle
LPC frame indicates start of a new cycle or termination of a
broken cycle.
LPC_DRQ0#
B8
PU 10K to 3.3V, not
support.
LPC_DRQ1#
B9
PU 10K to 3.3V, not
support.
LPC_SERIRQ
A50
I/O CMOS
3.3V / 3.3V
PU 10K to 3.3V
LPC serial interrupt
LPC serialized IRQ.
LPC_CLK
B10
O CMOS
3.3V / 3.3V
series 22
ƻ
resistor
LPC clock output - 33MHz nominal
LPC clock output 33MHz.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
CH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
SPI_CS#
B97
O CMOS
3.3V Suspend/3.3V
Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or
SPI1
Chip select for Carrier Board SPI – may be sourced from chipset
SPI0 or SPI1
SPI_MISO
A92
I CMOS
3.3V Suspend/3.3V
Data in to Module from Carrier SPI
Data in to Module from Carrier SPI
SPI_MOSI
A95
O CMOS
3.3V Suspend/3.3V
Data out from Module to Carrier SPI
Data out from Module to Carrier SPI
SPI_CLK
A94
O CMOS
3.3V Suspend/3.3V
Clock from Module to Carrier SPI
Clock from Module to Carrier SPI
SPI_POWER
A91
O
3.3V Suspend/3.3V
Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier Board.
Power supply for Carrier Board SPI – sourced from Module –
nominally 3.3V. The Module shall provide a minimum of 100mA
on SPI_POWER. Carriers shall use less than 100mA of
SPI_POWER. SPI_POWER shall only be used to power SPI
devices on the Carrier.
BIOS_DIS0#
A34
PU 10K
ɏ
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer
to for strapping options of BIOS disable signals.
BIOS_DIS1#
B88
PU 10K
ɏ
to 3V3 Suspend.
Selection strap to determine the BIOS boot device.
The Carrier should only float these or pull them low.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
CH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
VGA_RED
B89
O Analog
Analog
PD 150
:
to GND
Red for monitor. Analog DAC output, designed to drive a 37.5
ƻ
equivalent
load.
Red component of analog DAC monitor output, designed to drive
a 37.5
ƻ
equivalent load.
VGA_GRN
B91
O Analog
Analog
PD 150
:
to GND
Green for monitor. Analog DAC output, designed to drive a 37.5
ƻ
equivalent load.
Green component of analog DAC monitor output, designed to
drive a 37.5
ƻ
equivalent load.
VGA_BLU
B92
O Analog
Analog
PD 150
:
to GND
Blue for monitor. Analog DAC output, designed to drive a 37.5
ƻ
equivalent
load.
Blue component of analog DAC monitor output, designed to
drive a 37.5
ƻ
equivalent load.
VGA_HSYNC
B93
O CMOS
3.3V / 3.3V
Horizontal sync output to VGA monitor
Horizontal sync output to VGA monitor.
VGA_VSYNC
B94
O CMOS
3.3V / 3.3V
Vertical sync output to VGA monitor
Vertical sync output to VGA monitor.
VGA_I2C_CK
B95
I/O OD CMOS 3.3V / 3.3V
PU 2.2K
:
to 3.3V
DDC clock line (I2C port dedicated to identify VGA monitor capabilities)
DDC clock line (I2C port dedicated to identify VGA monitor
capabilities).
VGA_I2C_DAT
B96
I/O OD CMOS 3.3V / 3.3V
PU 2.2K
:
to 3.3V
DDC data line.
DDC data line.
Signal
Pin#
Pin Type
Pwr Rail /Tolerance
CH960 PU/PD
Module Base Specification R2.1 Description
COM Express Carrier Design Guide R2.0 Description
DDI
D26
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR0-
D27
DP1_LANE0- for DP / TMDS1_DATA2- for HDMI or DVI
DDI
D29
DP for DP / TMDS for HDMI or DVI
DDI1_PAIR1-
D30
DP1_LANE1- for DP / TMDS1_DATA1- for HDMI or DVI
DDI for Display Port: DP1_LANE 0 differential pairs
DDI for SDVO: SDVO1_RED± differential pair (Serial Digital Video red
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 2 differential pairs
O PCIE
AC coupled off Module
LPC multiplexed command, address and data.
LPC encoded DMA/Bus master request.
SPI Signals Descriptions
3.3V / 3.3V
LPC serial DMA request
I/O CMOS
3.3V / 3.3V
VGA Signals Descriptions
NA
Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping options
of BIOS disable signals.
LPC Signals Descriptions
I CMOS
I CMOS
LPC multiplexed address, command and data bus.
O PCIE
AC coupled off Module
DDI Signals Descriptions
DDI for Display Port: DP1_LANE 1 differential pairs
DDI for SDVO: SDVO1_GRN± differential pair (Serial Digital Video green
output)
DDI for HDMI/DVI: TMDS1_DATA lanes 1 differential pairs
