Denon DRA-100, Руководство по обслуживанию

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Pin Name Function Description
22 CH0_REF2 Output, tristate Channel 0 reference 2 output
23 CH0_REF1 Output, tristate Channel 0 reference 1 output
24 C0GND - Ground
25 C0P3V3 - 3.3 V I/O supply (quiet)
26 CH0_REF0 Output, tristate Channel 0 reference 0 output
27 C0P1V8 - 1.8 V core supply (quiet)
28 P1V8 - 1.8 V core supply
29 GND - Ground
30 P3V3 - 3.3 V I/O supply
31 CH3_PWM2 - Output Channel 3 high side drive
32 CH3_PWM1 - Bidirectional, pull-down Channel 3 high
side drive or channel 2/3 PWM sense
control
33 CH3_PWM0 - Output Channel 3 low side drive
34 CH2_PWM2 Output Channel 2 high side drive
35 CH2_PWM1 Bidirectional, pull-down Channel 2 high side drive or channel 2/3
PWM sense control
36 CH2_PWM0 Output Channel 2 low side drive
37 GND - Ground
38 P3V3 - 3.3 V I/O supply
39 CH1_PWM2 Output Channel 1 high side drive
40 CH1_PWM1 Bidirectional, pull-down Channel 1 high side drive or channel 0/1
PWM sense control
41 CH1_PWM0 Output Channel 1 low side drive
42 CH0_PWM2 Output Channel 0 high side drive
43 CH0_PWM1 Bidirectional, pull-down Channel 0 high side drive or channel 0/1
PWM sense control
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
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Direct Digital Feedback
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Data Sheet
Pin Name Function Description
44 CH0_PWM0 Output Channel 0 low side drive
45 P3V3 - 3.3 V I/O supply
46 GND - Ground
47 P1V8 - 1.8 V core supply
48 CH_0_1_AUDIO_SCK Input, pull-down Channels 0, 1 audio input bit clock
49 CH_0_1_AUDIO_SD Input, pull-down Channels 0, 1 audio input data
50 CH_0_1_AUDIO_WS Input, pull-down Channels 0, 1 audio input word clock
51 CH_2_3_AUDIO_SCK Input, pull-down Channels 2, 3 audio input bit clock
52 CH_2_3_AUDIO_SD Input, pull-down Channels 2, 3 audio input data
53 CH_2_3_AUDIO_WS Input, pull-down Channels 2, 3 audio input word clock
54 PWM_MODE Input, pull-down 2 wire vs 3 wire PWM mode control
55 GPIO_0 Bidirectional, pull-down GPIO
56 GPIO_1 Bidirectional, pull-down GPIO
57 P3V3 - 3.3 V I/O supply
58 GND - Ground
59 P1V8 - 1.8 V core supply
60 GPIO_2 Bidirectional, pull-down GPIO
61 INTERRUPT Output System interrupt
62 BRIDGE_ON Input, pull-down Bridge on/off control
63 RESET_BAR Input, pull-up Global reset
64 MCK_SEL Input, pull-down Master clock circuit select
65 GPIO_3 Bidirectional, pull-down GPIO
66 GND - Ground
67 P3V3 - 3.3 V I/O supply
68 GPIO_4 Bidirectional, pull-down GPIO
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
Page 17 of 181
CS-225959-DSP6
www.csr.com
CSRA6600
/
CSRA
6601
Direct Digital Feedback
A
m
plifier
Data Sheet
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