Denon DRA-100, Руководство по обслуживанию

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FL6300A (SMPS : IC821, IC831)
FL6300A Block Diagram
FL6300A Pin Discriptions
Pin Symbol Function
1 DET This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the following purposes:
- Generates a zero-current detection (ZCD) signal once the secondary-side switching current falls to zero.
- Produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant power
limit. The offset is generated in accordance with the input voltage when PWM signal is enabled.
- Detects the valley voltage of the switching waveform to achieve the valley voltage switching and minimize the
switching losses.
A voltage comparator and a 2.5 V reference voltage develop an output OVP protection. The ratio of the divider
determines what output voltage to stop gate, as an optical coupler and secondary shunt regulator are used.
2 FB The feedback pin should to be connected to the output of the error amplifier for achieving the voltage control loop. The
FB pin should be connected to the output of the optical coupler if the error amplifier is equipped at the secondary-side
of the power converter.
For primary-side control applications, FB is applied to connect a RC network to the ground for feedback-loop
compensation.
The input impedance of this pin is a 5 k equivalent resistance. A one-third (1/3) attenuator connected between the FB
and the PWM circuit is used for the loop-gain attenuation. FL6300A performs an open-loop protection (OLP) once the FB
voltage is higher than a threshold voltage (around 4.2 V) for more than 55ms.
3 CS Input to the comparator of the over-current protection. A resistor senses the switching current and the resulting voltage
is applied to this pin for the cycle-by-cycle current limit.
4 GND The power ground and signal ground. A 0.1 μF decoupling capacitor placed between VDD and GND is recommended.
5 GATE Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is
18 V.
6 VDD Power supply. The threshold voltages for startup and turn-off are 16 V and 10 V, respectively.
The startup current is less than 20 μA and the operating current is lower than 4.5 mA.
7 NC No connect.
8 HV High-voltage startup.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FL6300A • Rev. 1.0.2 2
Application Diagram
Figure 3. Marking Diagram
© 2
01
0
Fa
irc
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ld S
emi
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to
r C
or
poratio
n
w
w
w
.fai
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om
FL63
00
A
•
Re
v.
1.0
.2
3
Pi
n C
on
fig
ur
at
io
n
GND
DE
T
NC
CS
V
DD
1 2 3 4
8 7 6 5
FB
GATE HV
Fi
gu
re
4
.
Pin
A
ssi
gn
me
nt
s
Pin Defin
itio
ns
Pin #
Name
D
escr
ipt
io
n
1 D
ET
Th
is
p
in
is
c
on
ne
ct
ed
to
a
n
au
xi
lia
ry
w
in
di
ng
o
f t
he
tr
an
sf
or
m
er
v
ia
re
si
st
or
s
of
th
e d
iv
id
er
fo
r t
he
fo
llo
w
in
g p
ur
po
se
s:
-
G
en
er
at
es
a z
er
o-
curren
t d
et
ec
tio
n
(Z
C
D
) s
ig
nal
on
ce
th
e
se
con
da
ry
-s
id
e
sw
itc
hi
ng
c
urrent
fa
lls
to
z
er
o.
-
Pr
od
uc
es
an
o
ffs
et
volta
ge
to
comp
en
sat
e
the
th
re
sho
ld
v
ol
tag
e of th
e
pe
ak
current
li
mit
to
pr
ov
id
e a
c
on
st
an
t p
ow
er
li
m
it.
T
he
o
ffs
et
is
g
en
er
at
ed
in
a
cc
or
da
nc
e
w
ith
th
e
in
pu
t v
ol
ta
ge
w
he
n P
W
M
s
ig
nal
is
e
na
bl
ed
.
-
De
te
ct
s
the va
lle
y vo
ltag
e
of
the
s
w
itc
hi
ng
w
aveform
to
ac
hiev
e th
e
val
ley
volt
ag
e
sw
itc
hi
ng
an
d
m
in
im
iz
e
th
e s
w
itc
hi
ng
lo
ss
es
.
A v
ol
ta
ge
c
om
pa
rator
an
d a 2
.5
V
refe
re
nce
vo
ltag
e d
ev
el
op
an
o
utpu
t OV
P
p
ro
te
ction.
T
he
ratio
o
f the
di
vi
der
d
ete
rmin
es
what
o
utpu
t vo
lta
ge
to
s
to
p
ga
te,
a
s
an
op
tica
l c
ou
pl
er
a
nd
se
co
nd
ar
y s
hu
nt r
eg
ul
ato
r a
re
us
ed
.
2
FB
The f
eed
ba
ck
p
in
s
houl
d t
o be c
onn
ec
te
d
to th
e
ou
tp
ut o
f t
he
er
ro
r a
m
pl
ifie
r f
or
ac
hi
ev
ing
th
e
vol
tag
e
co
ntro
l loop
. T
he
FB
p
in
s
ho
ul
d be
c
onnect
ed
to t
he o
utp
ut
o
f the
op
tic
al
c
ou
pl
er if
th
e
erro
r amp
lif
ie
r i
s
eq
ui
ppe
d at
th
e
se
co
nd
ar
y-
si
de o
f t
he
po
w
er c
onv
er
te
r.
Fo
r pri
m
ar
y-
si
de
c
on
tro
l a
pp
lic
at
io
ns
, F
B
is
ap
pl
ie
d
to
co
nn
ect
a R
C
n
et
w
or
k to
th
e
gr
oun
d
fo
r
fe
ed
ba
ck
-lo
op
co
mp
en
satio
n.
The in
pu
t i
m
pe
danc
e of
th
is
pi
n
is
a
5 k
e
qu
iv
al
ent
res
is
tan
ce
. A
one
-thi
rd
(1
/3)
atte
nu
ator
conn
ec
te
d be
tw
ee
n th
e
FB
an
d
th
e PWM
c
irc
ui
t i
s
us
ed
fo
r t
he
lo
op
-ga
in
a
ttenu
at
ion.
F
L6300
A
pe
rfor
ms
an
ope
n-
loop
prot
ect
io
n (O
LP
) onc
e
the
F
B
v
ol
ta
ge
is
h
ig
he
r t
han
a
thre
sh
ol
d
vo
lta
ge
(aro
und
4.
2
V
) f
or
more
tha
n 5
5m
s.
3 CS
In
pu
t to
th
e
co
m
pa
rat
or
o
f th
e
ov
er
-cu
rre
nt
pr
ote
cti
on
. A
re
si
st
or
s
en
se
s
the
s
w
itc
hi
ng c
ur
ren
t
an
d
th
e
res
ulti
ng
v
ol
ta
ge
is
ap
pl
ie
d
to
this
p
in
fo
r the
c
ycle
-by
-c
yc
le
c
urren
t li
mi
t.
4 G
N
D
Th
e
po
w
er
gr
ou
nd
a
nd
s
ig
na
l g
rou
nd.
A 0.
1 µ
F
dec
ou
pl
ing
c
ap
ac
ito
r p
lac
ed
bet
w
ee
n
V
DD
an
d
GN
D
is
re
com
m
en
ded.
5 GA
TE
Tote
m-p
ole o
ut
put
genera
te
s
th
e
PW
M s
ig
nal
to
d
riv
e
the
e
xt
er
na
l po
w
er M
O
S
FET
. T
he
cl
am
ped
gat
e
outp
ut
v
ol
ta
ge
is 1
8 V.
6 V
DD
Po
w
er
s
up
pl
y. The
th
re
sho
ld v
ol
ta
ges
fo
r s
tart
up
a
nd t
urn-o
ff
ar
e
16
V
a
nd
1
0
V, r
es
pecti
vel
y.
The s
ta
rtu
p curre
nt
is
le
ss
th
an
20
µA
an
d
th
e
opera
ting
c
ur
re
nt
is
lo
w
er
th
an
4.
5
mA
.
7
NC
No
c
on
ne
ct
8
H
V
H
igh
-v
ol
ta
ge
s
ta
rtu
p
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FL6300A • Rev. 1.0.2 2
Application Diagram
Figure 3. Marking Diagram
77