Denon DRA-100, Руководство по обслуживанию

Страница: 49 / 98

SCHEMATIC DIAGRAMS (04/10)
SCH04_MAIN POWER
GND LINE POWER- LINE POWER+ LINE ANALOG AUDIO R ANALOG AUDIO L DIGITAL AUDIO SUBWOOFER
P/D
+5V
P/D
+5V
-9V
+9V
C
106
7
-
C
105
7
-
C
102
2
-
1V
8_C
Y92
0
C
108
7
-
5V_STB
Y
C
106
8
-
C
107
1
-
C
106
3
-
C
101
9
10000
N
-K
C
102
6
22000
N
-M
C
103
1
-
C
103
4
-
3V
3_C
Y92
0
C
107
9
-
C
104
1
1000
N
-K
CTR_PWR2
GND
GND
GND
GND
+12V
-32V
GND
+32V
R1086 10
R1063 10
C1015
-
C1013
100N-K
+32V
SMPS_+9V
5V_ANA
1V2_D
CTR_PWR2
2V5_FPGA
1V2_FPGA
1V2_DSP
3V3_DSP
GND
3V3_D
GND
18V_OLED
P/D
3V3_STBY
-9VA
GND
S1V8_CSR
R1V8_CSR
1V8_CSR
S3V3_CSR
5V25
+9VA
NGD
GND
+32V
R1073 10K
A_DC_PROT2
GND
3V3_STBY
CTR_PWR1
GND
+18V
R1062 10
C
100
1
100
N
-K
C1009
100N-K
R
100
1
-
-32V
C
106
4
-
C
106
6
1000
N
-K
R1037
100
C
105
6
1000
N
-K
R1030
1K
C
105
9
-
R1060
100
Q1008
PBSS5140U
R1032
10K
SMPS_-9V
18V_OLED
SMPS_+12V
R
104
2
5K
1-F
R
103
8
2K
4-F
R
103
9
1K
2-F
R
103
6
7K
5-F
R
102
9
7K
5-F
R
103
1
2K
4-F
CTR_PWR1
-32V
C1051
47/50(6.3*11)-RFO
C
101
8
10000
N
-K
BD1001
BKP_HS101-2125
2V5_FPGA
C
106
5
4700
N
-K
3V3_D
3V3_STBY
R
100
4
3K3
R1088
100
C
102
0
-
R1061
100
R
109
0
3K3
R1005
47K
R
100
9
1K C
102
3
100
N
-K
L1001
4.7UH
R
104
9
1K-F
R
108
7
7K
5-F
C
105
3
100
N
-K
R
101
3
10
K-F
C
102
7
-
R
101
1
7K
5-F
R
101
2
51
K-F
R
101
4
27
K
R
100
8
3K3
NGD
C
102
8
-
R1016
100
+5
VA
C
104
7
100/16
(6.3
*5.3
)-
R
V2
C
104
8
100
N
-K
C
104
3
100
N
-K
C
103
8
-
C
105
0
100
/6
.3
(6
.3
*5
.4
)-
U
Q
C
104
0
-
R
102
5
-
C
103
7
1000
N
-K
3V3_DIR
3V3_FPGA
5V_ADC
BD1022
0
5V_USB
BD1014
0
3V3_STBY
CTR_FPGA
GND
CTR_CSR
+9VA
+5VA
-5VA
R3V3_CSR
A3V3_CSR
C1V8_CSR
3V3_CSR
-32V
5V25_CSR
5V_STB
Y
R1010
100K
R
106
5
100
K
C
108
4
-
BD1026
0
C
107
6
-
BD1024
0
R1074
100K
R1071
100K
R
107
2
47
K
R1066
47K
3
VIN
1 GND
4
VFB
6 VBST
2
SW
5
EN
IC1014
TPS562200
3 VIN
1 GND
4 VFB
6 VBST
2 SW 5 EN
IC1012
TPS562200
D1005
LBAS16HT1G
R1076 10K
D1004
LBAS16HT1G
R1070
10K
D1002
LBAS16HT1G
R1069
10K
R
105
0
1K
A_DC_PROT1
1V8_CY920
2V5_CY920
3V3_CY920
C
100
7
100
N
-K
C
100
4
100
N
-K
C1011
100N-K
R
100
2
-
C
107
0
1000
N
-K
R1040
100
R
103
3
3K3
C
106
0
-
R1034
100
C
106
2
1000
N
-K
R
104
1
2K
4-F
R
103
5
2K
4-F
BD1002
BKP_HS101-2125
C
106
9
4700
N
-K
C
105
8
4700
N
-K
C
106
1
4700
N
-K
Q1001
BC807
1
6
3
4
2
5
Q1010
RAQ045P01
Q1018
PBSS5140U
C
102
5
22000
N
-M
ZD
100
1
LUDZS
5.
6BT
1G
R
105
5
1K
2-F
R1007
10K
C1055
10000N-K
C
104
4
100/16
(6.3
*5.3
)-
R
V2
C
103
3
1000
N
-K
C
102
9
-
C
103
0
1000
N
-K
C
103
6
-
2 GND
1
OUTPUT
3
INPUT
IC1006
NJM78L05UA
2 INPUT
1 COMMON 3 OUTPUT
IC1007
NJM79L05UA
C
104
6
100
/6
.3
(6
.3
*5
.4
)-
U
Q
C
103
2
4700
N
-K
C
103
5
4700
N
-K
R
102
6
1K
BD1011
BD102
R
106
4
100
K
C
108
0
10000
N
-K
C
108
6
1000
N
-K
C
108
3
-
C1090
10000N-K
C
102
1
-
C
102
4
10000
N
-K
C
107
8
1000
N
-K
C1075 10000N-K
R
106
7
100
K
R
107
5
47
K
C
107
4
-
D1003
LBAS16HT1G
R1068
10K
C
108
9
22000
N
-M
C
108
5
2200
N
-K
C1091
22000N-M
C1072
22000N-M
C
107
7
4700
N
-K
C
108
8
22000
N
-M
C
103
9
1000
N
-K
4 Ven
6 Vin
5 N/C
3 GND
1 Vout
2 N/C
7
GND
IC1004
LP5900SD
CTR_FPGA
CTR_3V3_DSP
C1017
470/16(10*12.5)-RFO
CPU POWER
-9VA
1V2_CY920
2V5_CY920
3V3_CY920
CTR_3V3_DSP
CTR_PWR1
CTR_3V3_CY920
CTR_2V5_CY920
CTR_1V2_CY920
R1078 -
R1052 100
CY920 POWER BLOCK
SMPS_+12V
SMPS_+9V
1V2_CY920
TO CPU/CY920 SHEET
CN1001
3P_WIRE
CTR_1V2_DSP
BD1017
0
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1010
AP7361-ADJ
BD1015
0
Q1009
RT1N141C
C1014
100/25(6.3*11)-RFO
C1010
220/50(10*16)-RFY
C
109
3
220
P-J
DSP/DIR/FPGA POWER BLOCK
CTR_FPGA
R
104
3
4K7
CTR_CSR
-9VA
Q1004
RT1N141C
R1027
3K3
R
102
8
3K3
R1089
10K
+9VA
R1003
10K
R
100
6
10
K
Q1003
BC817
C
105
2
100
N
-K
R
101
5
24
K
3 VIN
1 GND
4 VFB
6 VBST
2 SW 5 EN
IC1001
TPS562200
C
104
9
100
N
-K
Q1006
RT1N141C
C
104
5
100
N
-K
Q1005
PBSS5140U
C1042
-
BD1006
BKP_HS101-2125
R1021
1K
R
102
2
2K
4-F
BD1005
BKP_HS101-2125
R
102
0
3K-F
BD1004
BKP_HS101-2125
R
101
8
7K
5-F
BD1003
BKP_HS101-2125
1V8_CY920
CTR_1V2_DSP
CTR_PWR2
CTR_1V8_CY920
BD1010
BK_HS601
TO CSRA SHEET
R1023
1
BD1008
BK_HS601
R1058 100
R
105
9
10
K-F
BD1025
0
C
108
2
100
N
-K
R
105
3
2K
4-F
BD1023
0
C
107
3
100
N
-K
18V_OLED
Q1016
RT1N141C
Q1015
RT1N141C
SMPS_-9V
Q1013
RT1N141C
Q1014
RT1N141C
Q1012
RT1N141C
D1001
LBAS16HT1G
R
105
6
3K
6-F
R
108
5
10
K-F
R
104
7
9K
1-F
R
104
8
24
K-F
D'
B
S
P
M
S
M
O
RF
D'
B
S
P
M
S
M
O
RF
BD1016
0
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1011
AP7361-ADJ
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1008
AP7361-ADJ
BD1012
0
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1009
AP7361-ADJ
C1016
100N-K
C1012
220/50(10*16)-RFY
C
109
4
220
P-J
C1002
3300/35(18*40)-RFA
C1003
3300/35(18*40)-RFA
C1006
3300/35(18*40)-RFA
C1005
3300/35(18*40)-RFA
Q1011
RT1N141C
Q1002
RT1N141C
Q
100
7
2S
C
305
2
6
Vout
3
Vout
1
Vin
5
GND
2
Control
4
Vadj
IC1005
NJM2387ADL3
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1002
AP7361-ADJ
R1017
1K
R
101
9
2K
4-F
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1003
AP7361-ADJ
C
109
2
1000/16
(10
*20
)-
R
FO
BD1009
BK_HS601
R1024
1
C
108
1
-
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1015
AP7361-ADJ
R
105
7
5K
6-F
R
104
5
1K
1
EN
3
ADJ
5
OUT
4
IN
2
GND
IC1013
AP7361-ADJ
R
105
1
5K
1-F
L1002
3.3UH
L1003
2.2UH
R
105
4
10
K-F
R
104
6
10
K-F
6
5
3
2
1
4
10
13
14
12
11
7
8
9
CN1002
14P_WIRE
BD1019 0
TO PREOUT SHEET
BD1020 0
BD1021 0
BD1018 0
C1054
47/50(6.3*11)-RFO
TO DSP/DIR/FPGA SHEET
TO CPU/CY920 SHEET
TO SPKOUT SHEET
C
100
8
220/50(10*16)-RFY
DRA-100 MAIN - POWER (4/9)
A0
TO 0A
A1
TO 1A
A2
TO 2A
A3
TO 3A
A4
TO 4A
A5
TO 5A
A6
TO 6A
A7
TO 7A
A8
TO 8A
CN1001
TO CN221
CN1002
TO CN222
49
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16