A3V64S40GTP-60 Block Diagram
A3V56S30FTP
A3V56S40FTP
256M Single Data Rate Synchronous DRAM
Revision 1.1 Mar., 2010
Page 3 / 39
Note:This figure shows the A3V56S30FTP
The A3V56S40FTP configuration is 8192x512x16 of cell array and DQ0-15
Type Designation Code
A 3V
56
S40F TP-
G6
Speed Grade
75
:
133MHz@CL=3
7
:
143MHz@CL=3
6
:
166MHz@CL=3
G
:
Green
Package Type TP
:
TSOP (II)
Process
Generation
Function
Reserved
for
Future
Use
Organization
2
n
3
:
x8, 4
:
x16
SDR
Synchronous
DRAM
Density
56
:
256M bits
Interface
V
:
LVTTL
Memory
Style
(DRAM)
Zentel
DRAM
203
Содержание AVR-X7200W
Страница 8: ...Personal notes 8 ...
Страница 204: ...MX25L1606EM2I 12G DIGITAL U102 U202 U302 U402 MX25L1606EM2I 12G Block Diagram 8 PIN SOP 200mil 150mil BLOCK DIAGRAM 204 ...
Страница 210: ...NJW1194A INPUT U3203 U3204 BLOCK DIAGRAM 210 ...
Страница 211: ...2 FL DISPLAY FLD 17 BT 40GINK FRONT SPK Z6801 PIN CONNECTION GRID ASSIGNMENT Y2 q 211 ...
Страница 212: ...ANODE CONNECTION 212 ...