DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 19 of 242
The frequency of the low power oscillator is dependent on process variations within the IC, but is generally
somewhere in between 7,000 and 13,000 Hz. There are facilities within the IC to measure the length of an
LP oscillator cycle, in counts of the IC crystal oscillator divided by two, (i.e. this is 38.4 MHz ÷ 2, or 19.2 MHz).
2.4.1.1 Waking from sleep
and
Driving the
pin high for approximately 500 μs, (assuming the WAKE_PIN configuration bit is
set in
Sub-Register 0x2C:06 – AON_CFG0
Driving the
SPICSn
pin low for approximately 500 μs, (assuming the WAKE_SPI configuration bit is set
Sub-Register 0x2C:06 – AON_CFG0
). This can be achieved by doing a dummy SPI read of sufficient
length.
NOTE: When using the SPICSn pin to wake up the device it is important that the SPIMOSI line is
held low for the duration of the SPICSn
to ensure that a spurious write operation does not occur.
In addition return from
The internal sleep timer counter expires, (assuming the WAKE_CNT configuration is bit is set in
along with an appropriate SLEEP_TIM).
In all of three wakeup cases the device is returned to the
state by default but additional state
transitions can be automatically enacted thereafter depending on configurations.
2.4.1.2 Configuration register preservation
Prior to entering the
states and prior to exiting the
configurations are copied to and from an Always-On memory (AON). Power is maintained to AON memory
at all times, even in
states. The copying of configuration data (saving or restoring)
takes about 7 µs to complete. The detail of which configurations are saved and restored is given in
46: Configurations maintained in the AON
. Restoration of configurations during the
done if the ONW_LDC configuration bit is set in
7.2.45.1 – Sub-Register 0x2C:00 – AON_WCFG
Note: The host system should avoid SPI access to general system registers or OTP Memory during the
copying period to prevent any conflicts occurring
. Access to the TX (or RX) buffer is not restricted during this
period.
2.4.1.3 Automatically loading LDO calibration data from the OTP
When waking from
SLEEP
or
DEEPSLEEP
it is necessary to load the
been programmed during IC production test calibration. To confirm if the LDOTUNE_CAL has been
programmed first read the OTP address 0x4. If this reads back as non-zero (only the first byte needs to be
checked) then the device has been calibrated and the ONW_LLDO bit in
Sub-Register 0x2C:00 – AON_WCF
must
be set. This will allow the OTP parameter
to be automatically copied over to the
required register (
Sub-Register 0x28:30 – LDOTUNE
) each time the DW1000 wakes up. If the OTP address
0x4 reads back as zero, then the ONW_LLDO bit
must
not
be set.
