decaWave DW1000, Руководство пользователя

pin. This configuration bit enables the

line to bring the

DW1000 out of

states into operational mode. By default the WAKE_PIN

configuration is 1 enabling the

line as a wake-up signal. Setting the WAKE_PIN

configuration bit to 0 will mean that the

line cannot wake the DW1000 from

. See

NOTE

below on wakeup events.

WAKE_SPI

reg:2C:06

bit:2

Wake using SPI access. This configuration bit enables SPICSn to bring the DW1000 out of

into operational mode. By default the WAKE_SPI configuration is 1

enabling the SPICSn input as a wake-up signal. Setting the WAKE_SPI configuration bit to 0
will mean that SPICSn cannot wake the DW1000 form

below

on wakeup events.

WAKE_CNT

reg:2C:06

bit:3

Wake when sleep counter elapses. This configuration bit enables the sleep counter to bring the
DW1000 out of

into operational mode. By default the WAKE_CNT configuration is 1

enabling the sleep counter as a wake-up signal. Setting the WAKE_CNT configuration bit to 0
will mean that the sleep counter cannot wake the DW1000 form

Sub-Register 0x2C:0A – AON_CFG1

. See

NOTE

below on

wakeup events.

LPDIV_EN

reg:2C:06

bit:4

Low power divider enable configuration.  This bit enables a low power clock divider, that
allows and alternative source of clock for the sleep time counter. When LPDIV_EN is 0 the
sleep time counter counts cycles of the low powered ring oscillator. When LPDIV_EN is 1 the
sleep time counter counts cycles of the LP Clock.  See LPCLKDIVA below for details of this.
NOTE: While the LP Clock is more accurate than the low powered ring oscillator, it is thousands
of times more power hungry and, for this reason there are few applications that will use this.

LPCLKDIVA

reg:2C:06

bits:15–5

This field specifies a divider count for dividing the raw DW1000 XTAL oscillator frequency to set
an LP clock frequency.  This LP clock and LPCLKDIVA functionality is only enabled when the
LPDIV_EN configuration bit is set to 1.  The raw 38.4 MHz XTAL oscillator frequency input to
the LP clock divider is pre-divided by 2 to give a 19.2 MHz internal clock called XTI.   The
LPCLKDIVA field is 11-bits allowing divisors up to 2047 or LP clock frequencies down to 9.4 kHz.
An LPCLKDIVA value of 0 or 1 gives an LP clock frequency being the raw XTI frequency of 19.2
MHz.

SLEEP_TIM

reg:2C:06

bits:31–16

Sleep time. This field configures the sleep time count elapse value. The units of SLEEP_TIM
depend on which timer is running. When the low powered oscillator is running the units are
dependent on the oscillating frequency of the IC’s internal RING oscillator, which is between
approximately 7,000 and 13,000 Hz depending on process variations within the IC. This
frequency can be measured using the LPOSC_CAL (low-power oscillator calibration) control bit
in

so that sleep times can be more accurately set. If the

LPDIV_EN is set to 1 then the sleep time counter counts cycles of the LP Clock as set by the
LPCLKDIVA above. Note while this is a more accurate clock it is not recommended for general
sleeping as this has a much higher power consumption than the ring oscillator based sleep.

The SLEEP_TIM field is 16 bits wide, but represents the upper 16 bits of a 28-bit counter, i.e.
the low order bit is equal to 4096 counts. So, for example, if the ring oscillator frequency is
9500 Hz then programming the SLEEP_TIM with a value of 24 would yield a sleep time of 24 ×
4096 ÷ 9500, which is approximately 10.35 seconds.

NOTE: There are three mechanisms to wake the DW1000: using the

Sub-Register 0x2C:0A – AON_CFG1

line when the WAKE_PIN

configuration is 1, using SPICSn when the WAKE_SPI configuration is 1, and using the sleep timer
when the WAKE_CNT configuration is 1 and the sleep counter is enabled via the SLEEP_CEN bit in

. If none of these wakeup mechanisms are enabled and the

DW1000 is put into