D i d o H a r d w a r e M a n u a l
v . 1 . 0 . 5
independent interface (G/MII), reduced gigabit media
independent interface (RGMII), reduced media independent
interface (RMII), the management data input output (MDIO) for
physical layer device (PHY) management. DIDO provides two
ethernet ports, one Fast Ethernet with on-board PHY, and one
Gigabit Ethernet (GRMII only).
7.5.1
EMAC_RMREFCLK
EMAC_REFCLK signal is the reference clock for the internal
PHY (SMSC LAN8710) connected to EMAC[0] configured in
RMII mode. This signal is driven by the CPU and can be
optionally routed to J1.91 through a mount option. The
CPU.EMAC_RMREFCLK signal is internally split in two lines,
one connected to the internal PHY and the other routed to the
J1 connector; both lines are terminated with 22
Ω
resistors. For
more flexibility on using both EMAC[0] and EMAC[1]
interfaces, this signal has been routed to the J1 connector
providing the following configuration options:
●
generated internally (default configuration) and routed
externally for driving an external RMII PHY on the second
MAC (EMAC[1]) at 10/100 Mbit. In this case it is possible to
avoid the cost of an external crystal or oscillator.
●
generated by an external PHY mounted on the carrier board
(connected to EMAC[1]) and routed internally to the internal
PHY and CPU. In some cases this configuration could be
preferred.
7.5.2
Ethernet 10/100
On-board Ethernet PHY provides interface signals required to
implement the 10/100 Ethernet port. It is connected to
processor EMAC0 controller through RMII interface.
The following table describes the interface signals:
Pin name
Conn.
Pin
Function
Notes
EMAC0_PHY_LED_LINK/A
CT
J2.115 Link activity LED
Indication.
This pin is driven
active when a valid
link is detected and
blinks when activity
is detected.
August, 2014
56/78
