D i d o H a r d w a r e M a n u a l
v . 1 . 0 . 5
Pin name
Conn.
Pin
Function
Notes
TV_OUT1
J1.131
Composite/S-Video
(Luminance)
Amplifier Output
Configured as
“Normal mode”
(internal amplifier
used). This pin drives
the 75- TV
Ω
load.
TV_OUT2
J1.133
S-Video
(Chrominance)
Amplifier Output
Configured as
“Normal mode”
(internal amplifier
used). This pin drives
the 75- TV
Ω
load.
7.4
Digital Video Input ports
The HD Video Processing Subsystem supports two
independently configurable external video input capture ports
(VIP) up to 165MHz. Each video capture port supports one
scaler capable of both up and down scaling of one
non-multiplexed input stream; each video capture port supports
one programmable color space conversion to convert between
24-bit RGB data and YCbCr data. The VIP supports data
storage in RGB, 422, and 420 formats and each video capture
port channel supports chroma down-sampling (422 to 420) for
any non-multiplexed input data. The chroma down-sampling for
multiplexed streams is done as memory to memory operations
outside of HDVPSS on an individual frame data. Two VIP
instances are not identical from chip level. VIP instance 0 is a
24-bit interface and VIP instance 1 is a 16-bit interface. The
HDVPSS supports two independent pixel clock input domains
for each VIP, called Port A and Port B. Port A supports a single
up to 24 bit data bus at the instance level and Port B supports a
single 8 bit data bus at the instance level. The configuration for
each device input port is described in the following table:
Port A
Port B
8 bit
Off
16 bit
Off
24 bit
Off
8 bit
8 bit
August, 2014
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