D i d o H a r d w a r e M a n u a l
v . 1 . 0 . 5
ARM Cortex-A8 RISC processor, with Neon™
Floating-Point Unit, 32KB L1 Instruction Cache, 32KB L1
Data Cache and 512KB L2 Cache
CoreSight Embedded Trace Module (ETM)
ARM Cortex-A8 Interrupt Controller (AINTC)
Embedded PLL Controller (PLL_ARM)
●
PowerVR SGX 530 subsystem for vector/3D graphics
acceleration to support display and gaming effects
●
The HDVICP2 is a Video Encoder/Decoder hardware
accelerator supporting a range of encode, decode, and
transcode operations for most major video codec standards.
The main video Codec standards supported in hardware are
MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP,
RV9/10, AVS-1.0, and ON2 VP6.2/VP7.
●
The C674x DSP core is the high-performance floating-point
DSP generation in the TMS320C6000™ DSP platform and is
code-compatible with previous generation C64x Fixed-Point
and C67x Floating-Point DSP generation. The C674x
Floating-Point DSP processor uses 32KB of L1 program
memory with EDC and 32KB of L1 data memory. The DSP
has 256KB of L2 RAM with ECC, which can be defined as
SRAM, L2 cache, or a combination of both.
●
The high definition video processing subsystem (HDVPSS)
includes video/graphics display and capture processing
using the latest TI developed algorithms, flexible
compositing and blending engine, and a full range of
external video interfaces in order to deliver high quality
video contents to the end devices.
The following table shows a
comparison
between the devices,
highlighting the differences:
Processor DSP
3D
HDVICP HDVPSS Max clock
speed
DM8148
Yes
Yes
Yes
Yes
1 GHz
DM8147
Yes
n.a.
Yes
Yes
1 GHz
August, 2014
17/78
