12048321 Rev. 01 (Draft)
59
DATA MODUL AG | www.data-modul.com
J51
Pin
Signal / Function
Pin Type
Signal Description
8
RESET_KEY#
I (OD, 3.3V)
Reset button input. Active low request for the
embedded board to reset and reboot. Reset button
events can be generated and monitored
through the feature connector. This signal is being de-
bounced by the embedded board, tactive, in=25ms
9
CB_PWR_ON
O (CMOS 3.3V)
Carrier board circuits (apart from power management and
power path circuits) are not powered up until the module
asserts the CARRIER_PWR_ON signal.
10
SUS_CLK
O (CMOS 3.3V)
11
GND
GND
Connected to ground potential of the PCB
12
V_5V0_S0
Power
3.3V (S0) power supply for attached device (max.250mA)
13
WDTO#
O (CMOS 3.3V)
14
SLEEP#
I (OD 3.3V)
Sleep indicator from CB to SMARC module.
May be sourced from user Sleep button. Carrier to float
the line in in-active state. Active low,
level sensitive. Should be de-
bounced on the Module.
15
THERM#
IO (OD, 3.3V)
Indicates over-temp situations at some point on the
Embedded Board or within the embedded system.
Therm# events can be generated and monitored
through the feature connector.
16
LID#
O (OD)
LID switch. Used by the ACPI operating system to
detect an open or closed lid.
17
NC
NC
not connected
18
I2C_PM_ALERT#
IO (OD, 3.3V)
SMARC I2C_PM bus alert
19
I2C_GP_SDA
IO (OD, 3.3V)
SMARC I2C (GP) bus data line
20
I2C_GP_SCL
IO (OD, 3.3V)
SMARC I2C (GP) bus clock line
21
I2C_PM_SDA
IO (OD, 3.3V)
SMARC I2C (PM) bus data line
22
I2C_PM_SCL
IO (OD, 3.3V)
SMARC I2C (PM) bus clock line
23
GND
GND
Connected to ground potential of the PCB
24
V_RTCBAT
Power
Real-time clock circuit-power output. Nominally
+3.0V +/- 20mV ripple. V_RTCBAT is supplied from the
on board 3V DC-DC when the system is stanby powerded
or from the RTC Battery when the system is not powered.
Do not connect this signal to the battery without
protection.
25
GPIO0
IO (OD, 3.3V)
GPIO signal 0 from the SMARC embedded board. Default
direction is input.
26
GPIO1
IO (OD, 3.3V)
GPIO signal 1 from the SMARC embedded board. Default
direction is input
27
GPIO2
IO (OD, 3.3V)
GPIO signal 2 from the SMARC embedded board. Default
direction is input
28
GPIO3
IO (OD, 3.3V)
GPIO signal 3 from the SMARC embedded board. Default
direction is input
29
GPIO4 / HDA_RST#
IO (OD, 3.3V)
GPIO signal 4 from the SMARC embedded board. Default
direction is output.
GPIO4 is connected to HD-Audio Codec reset signal
when HD-Audio Codec is present.
