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12048231 Rev. 00 (Draft)
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4.20. LVDS Display Connector
Reference Designator: J30
Hirose DF20 connector with 50 positions, unshielded, straight
Description
LVDS Display Connector supporting single or dual channel flat panels with graphics resolution up to FHD (1080p).
Interfaces used
LVDS0 and LVDS1 from SMARC module
VDD Display Power Supply
The VDD power supply is
default
connected to VCC 5.0V (S0) by R393 resistor.
To change VDD to 3.3V (S0) voltage, remove R393 and populate R394.
Connector drawing and contact-numbering scheme
Figure 29 Connector
– J30
Pinout according to Data Modul Inhouse-Standard DMIS01
J30
Pin
Signal / Function
Pin Type
Signal Description
1
LVDS_GPIO1
IO (VDD)
LVDS 8/10bit Input Selection
LOW: 8bit / HIGH: 10bit
2
LVDS_GPIO2
IO (VDD)
LVDS Color Mapping
LOW: JEIDA / HIGH: VESA
3
LVDS_A0_N
O DP (LVDS)
LVDS Channel A (odd) pair 0, negative pin
4
LVDS_B0_N
O DP (LVDS)
LVDS Channel B (even) pair 0, negative pin
5
LVDS_A0_P
O DP (LVDS)
LVDS Channel A (odd) pair 0, positive pin
6
LVDS_B0_P
O DP (LVDS)
LVDS Channel B (even) pair 0, positive pin
7
GND
GND
Connected to ground potential of the PCB
8
GND
GND
Connected to ground potential of the PCB
9
LVDS_A1_N
O DP (LVDS)
LVDS Channel A (odd) pair 1, negative pin
10
LVDS_B1_N
O DP (LVDS)
LVDS Channel B (even) pair 1, negative pin
11
LVDS_A1_P
O DP (LVDS)
LVDS Channel A (odd) pair 1, positive pin
12
LVDS_B1_P
O DP (LVDS)
LVDS Channel B (even) pair 1, positive pin
13
GND
GND
Connected to ground potential of the PCB
14
GND
GND
Connected to ground potential of the PCB
15
LVDS_A2_N
O DP (LVDS)
LVDS Channel A (odd) pair 2, negative pin
16
LVDS_B2_N
O DP (LVDS)
LVDS Channel B (even) pair 2, negative pin
17
LVDS_A2_P
O DP (LVDS)
LVDS Channel A (odd) pair 2, positive pin
18
LVDS_B2_P
O DP (LVDS)
LVDS Channel B (even) pair 2, positive pin
