26
12048231 Rev. 00 (Draft)
DATA MODUL AG | www.data-modul.com
Pin
Signal / Function
Pin Type
Signal Description
Device/Connection
S74 US
O DP (USB SS)
Receive signal differential pairs for
USB Type-C or
S75 USB2_SSRX-
SuperSpeed on port 2 to module
J24 (upper port)
Key
S54 SATA_ACT#
O (OD 3.3V)
SATA activity indicator ( >24mA )
SATA Act. LED
S76 PCIE_B_RST#
I (CMOS 3.3V) PCIe port B reset input
J18 (M.2 Key-B)
S77 PCIE_C_RST#
I (CMOS 3.3V) PCIe port C reset input
USB3.0 Controller
S78 PC
O DP (PCIE)
Differential PCIe link C receive data pair
USB3.0 Controller
S79 PCIE_C_RX-
S80 GND
GND
Connected to ground potential of the PCB
GND
S81 PC
I DP (PCIE)
Differential PCIe link C transmit data pair
USB3.0 Controller
S82 PCIE_C_TX-
S83 GND
GND
Connected to ground potential of the PCB
GND
S84 PCIE_
I DP (PCIE)
Differential PCIe link B reference
J18 (M.2 Key-B)
S85 PCIE_B_REFCK-
clock input
S86 GND
GND
Connected to ground potential of the PCB
GND
S87 PC
O DP (PCIE)
Differential PCIe link C receive data pair
USB3.0 Controller
S88 PCIE_B_RX-
S89 GND
GND
Connected to ground potential of the PCB
GND
S90 PC
I DP (PCIE)
Differential PCIe link B receive data pair
J18 (M.2 Key-B)
S91 PCIE_B_TX-
S92 GND
GND
Connected to ground potential of the PCB
GND
S93 DP
I DP (TMDS)
Primary DP port differential
J28 DisplayPort
S94 DP0_LANE0-
Pair Data Lines
(IO Shield)
S95 DP0_AUX_SEL
O (CMOS 3.3V) Auxiliary selection
J28 DisplayPort
S96 DP
I DP (TMDS)
Primary DP port differential pair data lines
J28 DisplayPort
S97 DP0_LANE1-
(IO Shield)
S98 DP0_HPD
O (CMOS 1.8V) DP hot plug detect Input
J28 DisplayPort
S99 DP
I DP (TMDS)
Primary DP port differential pair data lines
J28 DisplayPort
S100 DP0_LANE2-
(IO Shield)
S101 GND
GND
Connected to ground potential of the PCB
GND
S102 DP
I DP (TMDS)
Primary DP port differential pair data lines
J28 DisplayPort
S103 DP0_LANE3-
(IO Shield)
S104
USB3_OTG_ID
O (CMOS 3.3V)
Output to indicate OTG Device Insertion on Port
3
not connected on
CB
S105
IO DP (LVDS)
Primary DP port bidirectional channel used for
link management and device control
J28 DisplayPort
S106 DP0_AUX-
(IO Shield)
S107
LCD1_BKLT_EN
I (CMOS 1.8V) Secondary LVDS Channel Backlight Enable
not connected on
CB
S108 L
I DP (LVDS)
Secondary LVDS channel diff. pair clock lines
J30
S109 LVDS1_CK-
S110 GND
GND
Connected to ground potential of the PCB
GND
S111
I DP (LVDS)
Secondary LVDS channel diff. pair data lines
J30
S112 LVDS1_0-
