12048321 Rev. 01 (Draft)
27
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Pin
Signal / Function
Pin Type
Signal Description
Device/Connection
S113 eDP1_HPD/DSI1_TE
O (CMOS 1.8V)
Detection of Hot Plug / Unplug of Secondary eDP
Display and Notification of the Link Layer
10k PD to GND
S114
I DP (LVDS)
Secondary LVDS channel diff. pair data lines
J30
S115 LVDS1_1-
S116
LCD1_VDD_EN
I (CMOS 1.8V) Secondary LVDS Channel Power Enable
not connected on
CB
S117
I DP (LVDS)
Secondary LVDS channel diff. pair data lines
J30
S118 LVDS1_2-
S119 GND
GND
Connected to ground potential of the PCB
GND
S120
I DP (LVDS)
Secondary LVDS channel diff. pair data lines
J30
S121 LVDS1_3-
S122
LCD1_BKLT_PWM
I (CMOS 1.8V) Secondary LVDS Channel Brightness Control
not connected on
CB
S123
GPIO13
IO (CMOS
1.8V)
Genera Purpose IO
not connected on
CB
S124 GND
GND
Connected to ground potential of the PCB
GND
S125
I DP (LVDS)
Primary LVDS channel diff. pair data lines
J30
S126 LVDS0_0-
S127 LCD0_BKLT_EN
I (CMOS 1.8V) Primary LVDS Channel Backlight Enable
J29
S128
I DP (LVDS)
Primary LVDS channel diff. pair data lines
J30
S129 LVDS0_1-
S130 GND
GND
Connected to ground potential of the PCB
GND
S131
I DP (LVDS)
Primary LVDS channel diff. pair data lines
J30
S132 LVDS0_2-
S133 LCD0_VDD_EN
I (CMOS 1.8V) Primary LVDS channel power enable
J30
S134 L
I DP (LVDS)
Primary LVDS channel diff. pair clock lines
J30
S135 LVDS0_CK-
S136 GND
GND
Connected to ground potential of the PCB
GND
S137
I DP (LVDS)
Primary LVDS channel diff. pair data lines
J30
S138 LVDS0_3-
S139 I2C_LCD_CK
I (CMOS 1.8V) I2C clock to read LCD display EDID EEPROMs
See I2C topology
S140 I2C_LCD_DAT
IO (CMOS
1.8V)
I2C Data to Read LCD Display EDID EEPROMs See I2C topology
S141 LCD0_BKLT_PWM
I (CMOS 1.8V) Primary LVDS Channel Brightness Control
J29
S142
GPIO12
IO (CMOS
1.8V)
General purpose IO
not connected on
CB
S143 GND
GND
Connected to ground potential of the PCB
GND
S144 eDP0_HPD/DSI0_TE
O (CMOS 1.8V)
Detection of hot plug / unplug of primary eDP
display and notification of the link layer
10k PD to GND
S145 WDT_TIME_OUT#
I (CMOS 1.8V) Watch-dog-timer output, low active
J51 LS to 3.3V
(Feature Connector)
S146 PCIE_WAKE#
IO (CMOS
1.8V)
PCIe wake up interrupt to host
– common to
PCIe links A, B, C, D
PCIE Devices and
Board Controller
STM32
S147 VDD_RTC
Analog (2.0 to
3.3V)
Low current RTC circuit backup power
– 3.0V
nominal
RTC Battery
