DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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3.1.4.
JTAG Test Access Port Pins
Signal Name:
JTRST
Signal Description:
IEEE 1149.1 Test Reset
Signal Type:
Input
This signal is used to asynchronously reset the test access port controller. At power up,
JTRST
must be
toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test
access port features. This pin has a 10k
W
pullup resistor. When FMS = 1, this pin is tied low internally.
Tie
JTRST
low if JTAG is not used and the framer is in DS21354/DS21554 mode (FMS low).
Signal Name:
JTMS
Signal Description:
IEEE 1149.1 Test Mode Select
Signal Type:
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various
defined IEEE 1149.1 states. This pin has a 10k
W
pullup resistor.
Signal Name:
JTCLK
Signal Description:
IEEE 1149.1 Test Clock Signal
Signal Type:
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
JTDI
Signal Description:
IEEE 1149.1 Test Data Input
Signal Type:
Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k
W
pullup resistor.
Signal Name:
JTDO
Signal Description:
IEEE 1149.1 Test Data Output
Signal Type:
Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected.
3.1.5.
Interleave Bus Operation Pins
Signal Name:
CI
Signal Description:
Carry In
Signal Type:
Input
A rising edge on this pin causes RSER and RSIG to come out of high-Z state and TSER and TSIG to start
sampling on the next rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of
data. This pin has a 10k
W
pullup resistor.
Signal Name:
CO
Signal Description:
Carry Out
Signal Type:
Output
An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER
and RSIG.
