S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
57
1.4.17 DFRWTR (Dual Flash Read Wait Register)
This section explains the DFRWTR.
In the dual flash mode (DFCTRLR:DFE=
”1”), this register is effective when ASZ="0b10" (32-bit read mode).
It configures the access method for the DualFlash area.
bit
7
6
5
4
3
2
1
0
Field
Reserved
DRWT
Attribute
RW
RW
Initial Value
1
1
[bit7:2] Reserved bits
The read values are undefined. Ignored on write.
[bit1:0] DRWT: Dual Flash Read Wait Cycle
Specifies the access method for flash memory.
Field
bit
Description
DRWT
1:0
Read Wait Cycle
00: 0 cycle wait mode (0 latency)
This setting can be used when HCLK is 72 MHz or less.
01: Setting prohibited
10: 4 cycles wait mode
This setting can be used when HCLK is 160MHz or less.
This setting must be used when HCLK is over 72 MHz.
11: 6 cycles wait mode (Initial value)
This setting must be used when HCLK is over 160 MHz
When HCLK is 72 MHz or less, 0 cycle wait mode (D
RWT = “0b00”) is suitable for CPU operation.
In DRWT=
”0b10” or DRWT=”0b11”, allowing operating the data buffer function. (See Section "
")
Notes:
−
Do not set DRWT to "0b00"(0 cycle wait mode) if HCLK exceeds 72 MHz.
While D
RWT setting is “0b00”, HCLK must not exceed 72 MHz.
−
Do not set DRWT to "0b10" if HCLK exceeds 160 MHz.
While D
RWT setting is “0b10”, HCLK must not exceed 160 MHz.
−
Perform a dummy read to register, after changing this register.
−
While dual flash mode is disabled (DFCTRLR : DFE=
”0”), writing to DFRWTR is prohibited.
