S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
32
Figure 1-10 Flash Accelerator Operating Flow (FRWTR.RWT=
”0b11”)
After a reset, RWT bits in FRWTR register becomes "0b11" to enter flash accelerator mode and operate the prefetch
buffer function but the trace buffer function has still been stopped. In order to activate this function, "1" must be written to
BE bit in FBFCR (Flash Buffer Control Register). See "
1.4.5 FBFCR (Flash Buffer Control Register)
)" for details.
Trace
Buffer
read
Prefetch
Buffer
read
Prefetch enable
Buffer hit
0 cyc.
Prefetch miss &
buffer hit
1 cyc.
Buffer miss
5 or 6 or 7 cyc.
Prefetch hit
0 cyc.
Prefetch miss &
buffer miss
4 or 5 or 6 cyc.
