Cypress MB95710M Series, Руководство пользователя

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MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 152 of 172
(V
CC
= 3.0 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
=
−
40 °C to
+
85 °C)
*1: R represents the pull-up resistance of the SCL and SDA lines, and C the load capacitance of the SCL and SDA lines.
*2: • See “Source Clock/Machine Clock” for t
MCLK
.
• m represents the CS[4:3] bits in the I
2
C clock control register ch.0 (ICCR0).
• n represents the CS[2:0] bits in the I
2
C clock control register ch.0 (ICCR0).
• The actual timing of the I
2
C bus interface is determined by the values of m and n set by the machine clock (t
MCLK
)
and the CS[4:0] bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz
<
t
MCLK
(machine clock)
<
16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < t
MCLK
≤
1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < t
MCLK
≤
2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < t
MCLK
≤
4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 MHz < t
MCLK
≤
10 MHz
(m, n) = (8, 22) : 0.9 MHz < t
MCLK
≤
16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < t
MCLK
(machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < t
MCLK
≤
4 MHz
(m, n) = (1, 22), (5, 4) : 3.3 MHz < t
MCLK
≤
8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 MHz < t
MCLK
≤
10 MHz
(m, n) = (5, 8) : 3.3 MHz < t
MCLK
≤
16.25 MHz
Parameter Symbol
Pin
name Condition
Value*
2
Unit Remarks
Min Max
START condition
detection
t
HD;STA
SCL,
SDA
R = 1.7 k
Ω
,
C = 50 pF*
1
2 t
MCLK
−
20 — ns
No START
condition is
detected when 1
t
MCLK
is used at
reception.
STOP condition
detection
t
SU;STO
SCL,
SDA
2 t
MCLK
−
20 — ns
No STOP condition
is detected when 1
t
MCLK
is used at
reception.
RESTART
condition detection
condition
t
SU;STA
SCL,
SDA
2 t
MCLK
−
20 — ns
No RESTART
condition is
detected when 1
t
MCLK
is used at
reception.
Bus free time t
BUF
SCL,
SDA
2 t
MCLK
−
20 — ns At reception
Data hold time t
HD;DAT
SCL,
SDA
2 t
MCLK
−
20 — ns
At slave
transmission mode
Data setup time t
SU;DAT
SCL,
SDA
t
LOW
−
3 t
MCLK
−
20 — ns
At slave
transmission mode
Data hold time t
HD;DAT
SCL,
SDA
0 — ns At reception
Data setup time t
SU;DAT
SCL,
SDA
t
MCLK
−
20 — ns At reception
SDA
↓ →
SCL
↑
(with wakeup
function in use) t
WAKEUP
SCL,
SDA
Oscillation
stabilization wait time
+
2 t
MCLK
−
20
— ns