Cypress MB91460, Руководство пользователя

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Document No. 002-05317 Rev. *C 1
AN205317
FR, MB91460, FR Clocks
The FR Family MCUs feature a sophisticated clock distribution scheme with the different clock sources such as RC
Clock, Main Clock, PLL Clock, Modulated PLL Clock, and Sub Clock. The core and the peripherals are connected to
different clock trees that can be connected to different clock sources and clock frequencies to allow for a fine-grained
control over the required operation speed and power consumption.
Contents
1 Introduction ............................................................... 1
2 Clock Tree ................................................................ 1
2.1 Overview ...................................................... 1
2.2 RC Clock ...................................................... 2
2.3 Main Clock ...................................................... 2
2.4 PLL Clock ...................................................... 2
2.5 Sub Clock ...................................................... 3
2.6 Clock Modulator ............................................... 3
3 Registers .................................................................. 5
3.1 Clock Source Control Register (CLKR) ............... 5
3.2 Clock Division Setting Register 0 (DIVR0) .......... 5
3.3 Clock Division Setting Register 0 (DIVR1) .......... 5
3.4 Clock Source Configuration Register (CSCFG) .. 6
3.5 Oscillation Control Register (OSCCR) ................ 7
3.6 PLL Control Registers (PLLDIVM) ...................... 7
3.7 PLL Control Registers (PLLDIVN) ....................... 7
3.8 PLL Control Registers (PLLDIVG) ...................... 8
3.9 PLL Control Registers (PLLMULG) ..................... 8
3.10 PLL Control Registers (PLLCTRL) ...................... 8
3.11 Clock Supervisor Control Register (CSVCR) ...... 9
3.12 Clock Modulator Control Register (CMCR) ....... 10
3.13 Clock Modulation Parameter Register (CMPR) 10
4 Using the start.asm ................................................ 11
5 Clock setup sequence ............................................ 13
5.1 Clock Setup Sequence (Example) .................... 14
6 Clock Modulator Configuration ............................... 17
7 Clocks Example ...................................................... 18
7.1 Starting Clock Modulator .................................. 18
7.2 Stopping Clock Modulator ................................. 18
8 Additional Information ............................................. 19
Document History ............................................................ 20
1 Introduction
The FR Family MCUs feature a sophisticated clock distribution scheme with the different clock sources such as RC
Clock, Main Clock, PLL Clock, Modulated PLL Clock, and Sub Clock. The core and the peripherals are connected to
different clock trees that can be connected to different clock sources and clock frequencies to allow for a fine-grained
control over the required operation speed and power consumption.
2 Clock Tree
The FR Family MCUs feature a sophisticated clock distribution that allows for fine-grained control over the used
clocks and frequencies. The details are given below.
2.1 Overview
The FR Family can be used with 2 different external clocks: the Main Clock and the Sub Clock and 1 internal (on-
chip) clock: the RC Clock. The external clocks may be connected to an oscillator, an oscillation circuit of a crystal and
capacitors, or an external clock supply. The internal RC Clock can be configured at 2 MHz or 100 kHz.
Internally, 4 different clocks are used: the core clock CLKB, the peripheral clock CLKP, External bus clock CLKT and
CAN clock CLKCAN. The CLKB provides the clock to the CPU. The CLKCAN provides the clock to the CAN
controllers. The CLKP provides the clock for all other peripherals.
Each of these four clocks features a separate prescaler. The following block diagram shows the clock distribution.