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Getting Started with EZ-BT WICED Modules
Document Number: 002-23400 Rev. **
67
A list of the available I/Os and supported functionality for each I/O of CYBT-353027-02 is shown in
Table 9. CYBT-353027-02 Module Available Connections and Functionality
Pad
Pad Name
Silicon Port Pin
Name
Functionality
UART
SPI
I2C
ADC
Coex
CLK/XT
AL
GPIO
OTHER
1
GND
GND
Ground
2
GPIO_4
GPIO_4/P1/
I2S_CLK/
PCM_CLK
SPI1_MISO/P1
(master)
IN28/P1
Yes (P1)
PCM_CLK
I2S_CLK
3
P11
P11/I2S_WS/
PCM_SYNC
IN24/P11
Yes (P11)
PCM_Sync
I2S_WS
4
P3
P3/I2S_DI/
PCM_IN
SPI1_CLK
(master)
SDA
Yes (P3)
PCM_DI
I2S_DI
5
XRES
RST_N
External Reset (Active LOW)
6
GPIO_5
BT_GPIO_5/
P8/P33
PUART_RX/P3
3
IN27/P8
IN6/P33
GCI_SE
CI_OUT
ACK1/P
33
Yes
(P8/P33)
7
SPI2_CS_N
SPI2_CSN
SPI2_CS_N
8
GPIO_0
BT_GPIO_0
Yes
(DevWake)
9
GPIO_1
BT_GPIO_1
Yes
(HostWake)
10
UART_TXD
BT_UART_TXD
HCI UART Transmit Data
11
CLK_REQ
BT_CLK_REQ
Used for shared-clock applications
12
UART_RXD
BT_UART_RXD
HCI UART Receive Data
13
VDDIN
VDDO
VDDIN (2.3 V ~ 3.6 V)
14
GND
GND
Ground
15
UART_RTS
BT_UART_RTS_N
HCI UART Request to Send Output
16
GPIO_3
BT_GPIO_3/P0
PUART_TX/P0
SPI1_MOSI/P0
(master)
IN29/P0
Yes (P0)
17
UART_CTS
BT_UART_CTS
HCI UART Clear to Send Input
18
GPIO_6
BT_GPIO_6/P9/
I2S_DO/
PCM_OUT
IN26/P9
Yes (P9)
I2S_DO
PCM_OUT
19
GND
GND
Ground
B . 2 . 2 H o s t R e c o m m e n d e d P C B L a y o u t
To assist in the host PCB layout design for CYBT-353027-02, Cypress provides three host PCB landing pattern
reference drawings in
, and
provides a dimensioned view of
provides the location to the center edge of each solder pad relative to the origin of the
module (upper right PCB outline).
provides the location to each solder pad center location for
the host PCB layout. Dimensions shown are in mm unless otherwise stated.