CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G
Page 24 of 28
Figure 18. MailBox Interrupt Timing
[57, 58, 59, 60, 61]
Switching Waveforms
(continued)
t
CH2
t
CL2
t
CYC2
CLK
L
t
CH2
t
CL2
t
CYC2
CLK
R
7FFFF
t
SA
t
HA
A
n+3
A
n
A
n+1
A
n+2
L_PORT
ADDRESS
A
m
A
m+4
A
m+1
7FFFF
A
m+3
R_PORT
ADDRESS
INT
R
t
SA
t
HA
t
SINT
t
RINT
Table 7. Read/Write and Enable Operation
(Any Port)
[1, 18, 62, 63, 64]
Inputs
Outputs
Operation
OE
CLK
CE
0
CE
1
R/W
DQ
0
–
DQ
35
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
D
IN
Write
L
L
H
H
D
OUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
Notes
57. CE
0
= OE = ADS = CNTEN = LOW; CE
1
= CNTRST = MRST = CNT/MSK = HIGH.
58. Address “7FFFF” is the mailbox location for R_Port of the 9-Mbit device.
59. L_Port is configured for Write operation, and R_Port is configured for Read operation.
60. At least one byte enable (BE0 – BE3) is required to be active during interrupt operations.
61. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
62. OE is an asynchronous input signal.
63. When CE changes state, deselection and Read happen after one cycle of latency.
64. CE
0
= OE = LOW; CE
1
= R/W = HIGH.
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