CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G
Page 9 of 28
IEEE 1149.1 Serial Boundary Scan (JTAG)
[23]
The FLEx36 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1-compliant TAPs. The TAP operates
using JEDEC-standard 3.3V IO logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V
DD
) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester must be configured to never enter the PAUSE-DR state.
Boundary Scan Hierarchy for 9-Mbit and 18-Mbit
Devices
Internally, the devices have multiple DIEs. Each DIE contains all
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below.
The scan chain for 9-Mbit and 18-Mbit devices uses a hierar-
chical approach as shown in
Figure 4
on page 10 and
Figure 5
on page 10. TMS and TCK are connected in parallel to each DIE
to drive all 2- or 4-TAP controllers in unison. In many cases, each
DIE is supplied with the same instruction. In other cases, it might
be useful to supply different instructions to each DIE. One
example would be testing the device ID of one DIE while
bypassing the rest.
Each pin of the devices is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This can be accom-
plished by merging the netlist of the devices with the netlist of the
user’s circuit board. To facilitate boundary scan testing of the
devices, Cypress provides the BSDL file for each DIE, the
internal netlist of the device, and a description of the device scan
chain. The user can use these materials to easily integrate the
devices into the board’s boundary scan environment. Further
information can be found in the Cypress application note
Using
JTAG Boundary Scan For System in a Package (SIP) Dual-Port
SRAMs
.
Notes
22. The “X” in this diagram represents the counter upper bits.
23. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
H
H
L
H
1 1
0s
1
0
1
0
1
0
1
0 0
Xs
1
X
0
X
0
X
0
1 1
Xs
1
X
1
X
1
X
1
0 0
Xs
1
X
0
X
0
X
0
Masked Address
Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 3. Programmable Counter-Mask Register Operation
[1, 22]
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