Document Number: 38-06076 Rev. *G
Revised Decenber 09, 2008
Page 28 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Document History Page
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Document Title: CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V FLEx36
™
3.3V
32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
Document Number: 38-06076
REV.
ECN NO.
Orig. of
Change
Submission
Date
Description of Change
**
232012
WWZ
See ECN
New data sheet
*A
244232
WWZ
See ECN
Changed pinout
Changed FTSEL# to FTSEL in the block diagram
*B
313156
YDT
See ECN
Changed pinout D10 from NC to VSS to reflect test mode pin swap, C10 from
rev[2,4] to VSS to reflect SC removal.
Changed tRSCNTINT to tRSINT
Added tRSINT to the master reset timing diagram
Added CYD01S36V to data sheet
Added I
SB5
and changed I
IX2
*C
321033
YDT
See ECN
Added CYD18S36V-133BBI to the Ordering Information Section
*D
327338
AEQ
See ECN
Change Pinout C10 from VSS to NC[2,5]
Change Pinout G5 from VDDIO
L
to REV
L
[2,3]
*E
365315
YDT
See ECN
Added note for V
CORE
Removed preliminary status
*F
2193427
NXR/AESA
See ECN
Changed t
CD2
and t
OE
Spec from 4ns to 4.4ns for -167.
Template Update.
*G
2623658
VKN/PYRS
12/17/08
Added CYD02S36VA-15AXC part
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