C
OMPACT
CHAMP-AV IV U
SER
’
S
M
ANUAL
C
URTISS
-W
RIGHT
C
ONTROLS
E
MBEDDED
C
OMPUTING
1-6
814256 V
ERSION
2 F
EBRUARY
2006
Each node connects to two adjacent nodes via a pair of PCI-X interfaces and provides an off-
board high-bandwidth Gigabit Ethernet connection. Each node has a separate 16-bit port
into the On-Board Interrupt and Control c(OBIC) FPGA, except for Node A, which has a 32-
bit port (see “On-Board Interrupt and Control (cOBIC)” on page 1-8 for details). With each
PowerPC having a dedicated bus to its own memory, application performance does not
degrade as it does in shared memory designs.
The processor bus between the MPC7448/MPC7447A and the Discovery III bridge operates
at a bus speed of 133 MHz and utilizes the PowerPC MPX mode of operation, providing higher
memory bus performance compared with the 60x bus.
Each processing node has two independent 64-bit, 100 MHz PCI-X connections, one to each
of the adjacent nodes. Separate, simultaneous transfers can occur on all four (QuadFlow) of
the PCI-X segments, resulting in a peak aggregate bandwidth of 3.2 GB/s. The peak PCI
bandwidth into any one node is 1600 MB/sec. High throughput translates to lower latencies
in application performance. Another advantage of the dual PCI-X connections at each node
is that transfers between adjacent nodes do not traverse a PCI-PCI bridge, and thus only one
PCI segment is used. This requires only a single PCI arbitration cycle, once again providing
minimum latency for data transfers. The Discovery™ III bridge features a highly
programmable arbitration controller which allows priority allocation between the processor,
PCI, and DMA engines for access to the DDR SDRAM memory. Users can fine tune the priority
of these devices to suit the needs of their application and achieve the best possible efficiency
of the memory subsystem.
Each Discovery™ III bridge provides four DMA controller engines which are capable of
transfering data between any of the bridges’ interfaces. The DMA capability is particularly
useful for managing transfers between processor node memory banks and transfers to and
from PMC devices. In addition, the Discovery III bridge provides two XOR DMA controller
engines that can read from up to eight sources, perform bitwise XOR between the eight
sources, and write the result to a destination.
These architectural advantages of the Compact CHAMP-AV IV will simplify and speed the
process of application development. Developers can focus on the problem, rather than
optimizing for board architectures that restrict data flow to one or two simultaneous
transactions. The memory map of the Compact CHAMP-AV IV allows any processor to access
the memory of any other processor and both PMC sites. Any PMC module can access any of
the processor node memories.
N
ODE
E P
ROCESSOR
The Compact CHAMP-AV IV includes a fifth processor, called Node E. This processor, an
MPC8540, is a highly integrated device that contains a DDR SDRAM controller, PCI-X
interface, local bus (similar to Disco III device bus), Gigabit Ethernet MAC and UART on chip.
The 8540 can be used in a wide variety of applications as a control and management
interface, traffic manager, or other function. This capability allows the other nodes to focus
on more processing-intensive applications.
The 8540 can access all the memory of the other nodes and both PMCs over the PCI-X bus.
It also has its own interface into the cOBIC so that all the features of the cOBIC are available
to this device as well.
D
OUBLE
D
ATA
R
ATE
SDRAM
Each 7448/7447A processor node on the Compact CHAMP-AV IV consists of either 256 or
512 Mbytes of Double Data Rate (DDR) SDRAM. The instantaneous peak data transfer rate
to the DDR-266 SDRAM is over 2.0 GB/s at 133 MHz. The DDR SDRAM is accessible from the
processor and from both PCI buses.
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