C
URTISS
-W
RIGHT
C
ONTROLS
E
MBEDDED
C
OMPUTING
P
RODUCT
O
VERVIEW
814256 V
ERSION
2 F
EBRUARY
2006
1-19
R
ESET
The Compact CHAMP-AV IV has the following reset capabilities:
• front panel reset button
• capability to be reset via software (front panel reset emulation)
• J4 reset pin (PBRST on J4 Row D pin 1). Grounding this pin is equivalent to activating
the front panel reset.
• Individual processor reset through the Boot Monitor.
• cPCI system reset
T
IMERS
The Compact CHAMP-AV IV board provides a large number of timing resources to facilitate
precise timing and control of system events. A list of available timers is given in Table 1.5
below.
T
EMPERATURE
/V
OLTAGE
S
ENSORS
The Compact CHAMP-AV IV provides sensors to monitor board temperatures and voltage
levels. The sensors allow six temperatures and six voltages to be measured. The sensors
can generate an interrupt based on programmable high and low voltage and temperature
thresholds. The Board Support Library functions will allow the user to read the sensors at
any time and to program the sensor's threshold values.
The Compact CHAMP-AV IV has two temperature/voltage sensor Integrated Circuits (ICs)
installed on the back of the board (Maxim MAX6656). The ICs are located at locations U225
and U229 (see Figure 1.9 on page 1-22). In revision A of the Compact AV-IV baseboard, the
sensors are connected to Node A of the Discovery III bridge. In revision B (and later) of the
Compact AV-IV baseboard, the sensors are connected to both Node A of the Discovery III
bridge, as well as to the MPC8540. Each sensor IC is capable of measuring three
temperatures, one local temperature and two remote temperatures. The local temperature
is the temperature of the card at the IC's location. The remote temperatures are the die
temperatures of the 7448/7447A PowerPC processors. Sensor U225 can measure its own
temperature and the die temperature of processors A and D. Sensor U229 can measure its
own temperature and the die temperature of processors B and C. The local and remote
T
ABLE
1.6:
Timing Resources
Timer Facility
Implementation
Type
Size
Tick Rate / Period
Maximum Duration
PowerPC
CPU
Free-running counter
64 bit
33.25 MHz / 30 ns
(at 133 MHz Bus
Speed)
17,548 years
Time Base
Register
Implementation
Type
Size
Tick Rate / Period
Maximum Duration
PowerPC
CPU
Presettable, readable
(counts up)
32 bit
33.25 MHz / 30 ns
128.8 seconds
Decrementers
Implementation
Type
Size
Tick Rate / Period
Maximum Duration
General Purpose
# 0-3
Discovery III
Presettable, readable
(counts down)
32 bit
125.0 MHz / 8 ns
34.3 seconds
Watchdog Timers
(one per CPU)
cOBIC (FPGA)
Presettable, readable
(counts down)
24 bit
1 MHz / 1
µ
S
16.7 seconds
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