C
OMPACT
CHAMP-AV IV U
SER
’
S
M
ANUAL
C
URTISS
-W
RIGHT
C
ONTROLS
E
MBEDDED
C
OMPUTING
1-12
814256 V
ERSION
2 F
EBRUARY
2006
The
DVx_PCI_INT
[1:0] interrupts from each node are actually the PCI interrupts from the
Discovery part. Through interrupt steering registers in the Discovery, interrupts from
various MV64460 resources (DMA, Timers, etc.) can be mapped to these outputs.
TALERAD
and
TALERBC
provide over temperature alarm information to the cOBIC. The
sensors that generate these alarms are located at U225 and U229.
TALERBC
originates from
U229 while
TALERAD
originates from U225 (see Figure 1.9 on page 1-22).
Each temperature sensor monitors three separate temperatures.
TALERBC
monitors the
temperature of processor B, processor C, and the temperature of the board at the location
of U23 (location of itself).
TALERAD
monitors the temperature of processor A, processor D,
and the temperature of the board at the location of U19 (location of itself).
Inter-Processor
Module
In multi-processor applications, software designers implement message passing schemes
between the various processors in the system. The most common implementation is for the
transmitting processor to cause an interrupt to occur on the receiving processor, with a pre-
agreed protocol between the pair to define the location and content of the message.
The problem with this mechanism is that many board architectures suffer latencies and other
slowdowns because the same PCI bus that is used for inter-processor data transfers is also
used for passing these interrupts. The Compact CHAMP-AV IV has special purpose hardware
to accelerate inter-processor messaging. This hardware is contained in the inter-processor
module and consists of processor to processor mailbox interrupts and hardware-controlled
interrupt routing facilities.
The inter-processor module consists of five FIFOs for support of mailbox interrupts, five
inter-processor interrupt registers, sixteen semaphore registers, five watchdog timers and a
multi-board synchronous timer. These features are described below:
Mailbox Interrupts
The cOBIC provides mailbox interrupts, whereby a processor can interrupt another processor
and deliver a 16-bit value. Each processor has a 16-bit, 32-deep FIFO. Any processor can
write to the FIFO of any other processor. An entry in the FIFO causes an interrupt to the
associated processor, if enabled. The software can use the 16-bit value to include a message
with the interrupt. The combination of a separate data path and the inclusion of a 16-bit
message can significantly reduce the latency of using interrupts to send messages between
processors.
Inter-processor Interrupts
The Inter-Processor Module also contains the Inter-Processor Interrupt generation registers.
Typically the external interrupts are not latched in cOBIC since they are latched at the
source. However, the interrupts generated from Inter-Processor Interrupt generation
registers (IPI) are latched. The IPI generation register has two primary fields to consider
(see Table 1.3). A three-bit Processor ID field defines the processor to be interrupted and a
three-bit field that defines the Processor Interrupt Identification value. To use the register,
GPIO[2:1]
Edge (Rising or
Falling) or Level
(Active Low or High)
Source
User Interrupts from cPCI connector J4, pins B25 and
D25.
TALERAD
Active low
cOBIC
Overtemperature alarm from Nodes AD sensor (not cur-
rently implemented)
TALERBC
Active low
cOBIC
Overtemperature alarm from Nodes BC sensor (not cur-
rently implemented)
INT_88E1111
Ethernet interrupt from node E Phy (not currently imple-
mented)
P[3:0]_INT_88E1145
Ethernet interrupts from nodes A-D Phy (not currently
implemented)
T
ABLE
1.2:
External Interrupt Sources (Continued)
Interrupt Input
Detection Mode
Location for
Clearing
Description
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