Creotech FMC masterFIP, Руководство пользователя

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internal FPGA pulldown.
IC1 output should be is Hi-
Z.
#6 1 0 0 High
Read "0" from the FPGA
EXT_SYN pin forced by
internal FPGA pulldown.
IC1 output should be is Hi-
Z. No matter voltage forced by
USB Relay Box value read by
FPGA is constant.
OEn line is checked.
#7 0
1
(output)
0 Low
Read "0" from the FPGA
EXT_SYN pin forced by
internal FPGA pulldown.
IC1 output should be is Hi-
Z.
#8 0 1 0 High
Read "0" from the FPGA
EXT_SYN pin forced by
internal FPGA pulldown.
IC1 output should be is Hi-
Z.
IC1 buffer direction is
changed to output, causing
port connected with FPGA to
go Hi-Z.
FPGA IO is kept in Hi-Z state
(with internal pulldown).
If switching buffer direction
didn’t work, value read from
FPGA IO would follow USB
Relay Box voltage (as shown
in previous tests).
EXT_SYNC_DIR line checked.
Possible errors:
o
Bad connections to the USB relay box
o
Bidirectional buffer (IC1) might be badly soldered
o
LEMO port might be badly soldered
o
Faulty soldering of FMC connector
Test 04
DS18B20 (IC11) thermometer verification.

Read unique ID

Verify ID correctness

Take a temperature measurement
Possible errors:

Get ID from DS18B20, DS18B20 ID verification, temperature measurement
o
Thermometer might be broken or badly soldered
o
Faulty soldering of FMC connector
Test 05
24AA64T (IC10) serial EEPROM test.

Write and verify some data patterns

Generate and write following sdbfs files to EEPROM: