Creative BLASTER PC M004, Руководство пользователя

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Memory Configuration and BIOS Settings 6-13
Video BIOS
Cacheable
Allows the user to specify the system BIOS
C000-C7FF area as cacheable or non-cacheable.
The Enabled setting yield better performance but
poses the danger of system errors if programs are
written to this memory area.
Video RAM
Cacheable
This is a new cache technology for the CPU’s
video memory. By caching the display data, the
display speed can be greatly improved. However,
if your display card cannot support this feature,
you must disable this item. Otherwise, your
system may not boot up.
8 Bit I/O Recovery
Time
This is the length of time, measured in CPU
clocks, which the system will delay after the
completion of an 8 bit input/output (I/O) request.
This delay is necessary for the CPU to recover
from completing the I/O request. This item
allows you to specify the amount of recovery time
allowed for 8 bit I/O. The setting can be NA, or 1
to 8 CPU clocks.
16-Bit I/O Recovery
Time
Allows you to specify the amount of recovery
time allowed for 16 bit I/O requests. The setting
can be NA, or 1 to 4 CPU clocks.
Memory Hole at
15M-16M
Some special add-on cards require a 1 MB
address space between 15 MB and 16 MB. Verify
with the documentation that comes with the
card(s) to see if you need this address space.
Passive Release
If this is enabled, the chipset will provide a
programmable passive release mechanism to
meet the required ISA master latencies.
Delayed Transaction
Since PCI specification version 2.1 requires much
tighter controls on target and master latency, PCI
cycles to or from ISA typically take longer. If this
item is enabled, the chipset will provide a
programmable delayed completion mechanism to
meet the required target latencies.
Table 6-6: The Chipset Features Setup Screen items.
Item Description