Contec DAI12-4FITGY, Руководство пользователя, Страница: 33 / 65

Using the I/O Address Map
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DAI12-4(FIT)GY
Details on the Analog Output Status
The analog output status indicates the status of the D/A conversion operation.
Figure 4.14. Analog Output Status
Dataset Busy (DSB) [D0]:
When this bit is [0], the dataset is available for the output of D/A conversion data.
When this bit is [1], the dataset is writing data to a D/A converter register in the module
and is unavailable for writing any other D/A conversion data.
End of Conversion (EOC) [D2]:
When [1] is set to this status bit, the data that has been written to the D/A converter is
converted into analog signals. This bit is cleared when [1] is set to the End of
Conversion Status of the analog output status reset port.
The end of conversion does not include analog signal setup time. *
Pacer Clock Input Status [D4]:
[1] is set to this status bit when a pacer clock is input after the timer start command is
issued in the clock mode. This bit is cleared when [1] is set to the clock input status
bit for the analog output status reset port. *
D7 D6 D5 D4 D3 D2 D1 D0
input
+22
(16h)
Analog Output Status
Pacer
Clock Error
End of
Conversion
0 0 0 0
Pacer
Clock Input
Data Set
Busy
D7 D6 D5 D4 D3 D2 D1 D0
output
+22
(16h)
Status Reset
Pacer
Clock Error
End of
Conversion
0 0 0 0 0
Pacer
Clock Input
Starting
I/O Address