Contec DAI12-4FITGY, Руководство пользователя, Страница: 29 / 65

Using the I/O Address Map
24
DAI12-4(FIT)GY
Setting an Internal Pacer Clock
When either the "clock mode" or the "internal pacer clock" is selected as a D/A
conversion condition, this step specifies a clock cycle (clock data). In the initialized
state, the clock data is undefined. When using an internal pacer clock, you must set
the requisite clock data.
Clock data is specified in 250-nsec increments.
The allowable range is 10,000nsec - 1,073,741,824,000nsec (approximately 17 minutes
54 seconds), which corresponds to 39 - 4,294,967,295 setup data.
The relationship between clock cycles and setup data can be expressed in the following
formula:
Pacer clock
250
Clock data = -1
The pacer clock is specified in units of nanoseconds.
The value of the pacer clock must satisfy the following expression:
D/A conversions in accurate cycles cannot be performed if the specified value is less
than the conversion time for a specified number of channels.
The internal pacer clock-setting control port assumes the following state:
Figure 4.11. Setting an Internal Pacer Clock
Pacer clock 10000nsec x Number of specified channels
(10
µ
sec)
D7
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0
Command
0 0 0 0 0 1 0 0
output
+24
(18h)
output
+28
(1Ch)
Timer
Data 07
Timer
Data 06
Timer
Data 05
Timer
Data 04
Timer
Data 03
Time r
Data 02
Timer
Data 01
Timer
Data 00
+29
(1Dh)
Timer
Data 15
Timer
Data 14
Timer
Data 13
Timer
Data 12
Timer
Data 11
Timer
Data 10
Timer
Data09
Timer
Data08
+30
(1Eh)
Timer
Data 23
Timer
Data 22
Timer
Data 21
Timer
Data 20
Timer
Data 19
Timer
Data 18
Timer
Data 17
Timer
Data 16
+31
(1Fh)
Timer
Data 31
Timer
Data 30
Timer
Data 29
Timer
Data 28
Timer
Data 27
Timer
Data 26
Timer
Data 25
Timer
Data 24
Timer Data 0
Timer Data 1
Timer Data 2
Timer Data 3
Starting
I/O Address