Contec CNT24-2GY, Руководство пользователя

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3. Setup
26 CNT24-2(USB)GY
Clearing Count Value
Asynchronous clear
The counter is zero-cleared when phase-Z is input, irrespective of the input state of
phase-A or B.
When phase-Z is set to positive logic, HIGH level is effective signal; When it is set to
negative logic, LOW level is effective signal. The timing chart is shown below
corresponding to the following settings.
Counter mode: 2-phase input, 1 multiplier
The setting of the phase-Z input logic: positive logic
The setting of the rotary direction (DIR): CW
Figure 3.11. Asynchronous Clear
Synchronous clear
Set the rotary direction of the encoder to clockwise, the counter is zero-cleared when
phase-A rises. As same with asynchronous clear, when phase-Z is set to positive
logic, HIGH level is effective signal; When it set to negative logic, LOW level is
effective signal. The timing chart is shown below corresponding to the following
settings.
Counter mode: 2-phase Input, 1 multiplier
The setting of the phase-Z input logic: positive logic
The setting of the rotary direction (DIR): CW
Figure 3.12. Synchronous Clear
Phase-A
Phase-B
(Phase-A/UP)
(Phase-B/DOWN)
Count data
4 5 0 1
(Phase-Z/CLR)
Phase-Z
7
Phase-A
Phase-B
(Phase-A/UP)
(Phase-B/DOWN)
Count data
4
5 7 0 1
(Phase-Z/CLR)
Phase-Z