Contec BUF-PCI(98), Руководство пользователя

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Programming
BUF-PCI(PC), BUF-PCI(98)
75
Interrupt Procedure
One interrupt request level is assigned from the PC to the
BUS-PCI(PCI) board. For this reason, the BUF-PCI(PCI) board
detects multiple interrupt request signals generated on the I/O
expansion unit one by one. If there is even just one interrupt request,
the interrupt request signal is output to the PCI bus to request the PC for
interrupt.
With the control port of the BUS-PCI(PCI) board, you can set the mask
to specify enabling or disabling of an interrupt signal generated on the
I/O expansion unit. Interrupt can be generated only with an interrupt
request signal at a non-masked level.
The PCI bus specifications allow sharing of an interrupt request level
with another system. As a result, a program that processes interrupt
requests needs to determine whether or not the interrupt request has
been issued by the BUS-PCI(PCI) board in the interrupt handler.
In order to allow making this decision and verifying the level at which
the interrupt request is generated on the I/O expansion unit, there are a
status register to verify whether or not there is an interrupt request
signal and a port to reset that status register.
(1) In the main routine, set the interrupt request mask register.
(2) In the main routine, reset the interrupt request status register.
(3) In the main routine, specify PC settings needed to handle
interrupts, such as the interrupt handler.
(4) When an interrupt request generates on the PCI bus, processing
moves to the interrupt handler to check the interrupt request status
in the non-masked bit and to see if status is set. If it is set, the
interrupt request is considered to be of the BUS-PCI(PCI) board
and is processed.
(5) If the interrupt request is from the BUS-PCI(PCI) board, reset the
interrupt request status register to allow monitoring of the level at
which the next interrupt request is generated on the I/O expansion
unit.