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AN202
V1.0 | Page 19/73
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used for subsequent chip upgrading.
4.1.3
TMR0
(
Addr:0x01
)
Table 4-3. TMR0 Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TMR0
Timer0<7:0>
,
Count result register
Reset
X
X
X
X
X
X
X
X
Type
RW
4.1.4
STATUS
(
Addr:0x03
)
Table 4-4. STATUS Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
STATUS
-
-
PAGE
/TF
/PF
Z
HC
C
Reset
-
-
0
1
1
X
X
X
Type
-
-
RW
R
R
RW
RW
RW
Table 4-5. STATUS Bit Function Description
Bit
Name
Function
7:6
-
No function, read as
“0”
5
PAGE
Register Bank Select bit:
0 = BANK0
(
00h-7Fh
)
1 = BANK1
(
80h-FFh
)
4
/TF
Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occured.
3
/PF
Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By executation of the SLEEP instruction
2
Z
Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
1
HC
Half-carry/
bit(ADDWF
、
ADDLW
、
SUBLW
、
SUBWF instructions)
1 = A carry/
from the 4
th
low-order bit of the result occurred
0 = No carry/
from the 4
th
low-order bit of the result occurred
0
C
Carry/
bit(ADDWF
、
ADDLW
、
SUBLW
、
SUBWF instructions)
1 = A carry/
from the Most Significant bit of the result occurred
0 = No carry/
from the Most Significant bit of the result occurred
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