Clevo W243HVQ Series, Руководство по обслуживанию

Страница: 63 / 105

Schematic Diagrams
PROCESSOR/ RESERVED B - 9
B.Sch
e
m
a
tic D
iag
rams
PROCESSOR/ RESERVED
V R E F _C H _ A _ D I M M
R 40 * 0_ 0 4
MV R E F _ D Q _D I M0
R 44 * 0_ 0 4
MV R E F _ D Q _ D I M 1
Q 7
* A O3 4 02 L
G
D S
R 2 8
1 K _1 % _ 0 4
R 4 9
*1 K _ 04 R 2 9
1 K _1 % _ 0 4
Q 6
* A O3 4 02 L
G
D S
R 3 9
*1 K _ 04 R 3 1
1 K _ 1 % _0 4
R 3 8
1 K _ 1 % _0 4
D R A MR S T _C N T R L 3 , 1 4
1 . 5 V
1. 5 V
M V R E F _ D Q_ D I M MA 9
D R A MR S T _C N T R L
M V R E F _ D Q_ D I M MB 1 0
V R E F _C H _ B _ D I M M
RE
SE
RV
ED
U 3 4 E
P Z 9 8 82 7 -3 64 B -0 1 F
C F G [ 0]
A K 2 8
C F G [ 1]
A K 2 9
C F G [ 2]
A L 2 6
C F G [ 3]
A L 2 7
C F G [ 4]
A K 2 6
C F G [ 5]
A L 2 9
C F G [ 6]
A L 3 0
C F G [ 7]
A M 3 1
C F G [ 8]
A M 3 2
C F G [ 9]
A M 3 0
C F G [ 10 ]
A M 2 8
C F G [ 11 ]
A M 2 6
C F G [ 12 ]
A N 2 8
C F G [ 13 ]
A N 3 1
C F G [ 14 ]
A N 2 6
C F G [ 15 ]
A M 2 7
C F G [ 16 ]
A K 3 1
C F G [ 17 ]
A N 2 9
R S V D 3 4
A M 33
R S V D 3 5
A J 2 7
R S V D 3 8
J 1 6
R S V D 4 2
A T 3 4
R S V D 3 9
H 1 6
R S V D 4 0
G1 6
R S V D 4 1
A R 35
R S V D 4 3
A T 3 3
R S V D 4 5
A R 34
R S V D 5 6
A T 2
R S V D 5 7
A T 1
R S V D 5 8
A R 1
R S V D 4 6
B 3 4
R S V D 4 7
A 3 3
R S V D 4 8
A 3 4
R S V D 4 9
B 3 5
R S V D 5 0
C 3 5
R S V D 5 1
A J 3 2
R S V D 5 2
A K 3 2
R S V D 3 0
A E 7
R S V D 3 1
A K 2
R S V D 2 8
L 7
R S V D 2 9
A G 7
R S V D 2 7
J 1 5
R S V D 1 6
C 3 0 R S V D 1 5
D 2 3
R S V D 1 7
A 3 1
R S V D 1 8
B 3 0
R S V D 2 0
D 3 0 R S V D 1 9
B 2 9
R S V D 2 2
A 3 0 R S V D 2 1
B 3 1
R S V D 2 3
C 2 9
R S V D 2 4
J 2 0
R S V D 3 7
T 8
R S V D 6
B 4
R S V D 7
D 1
R S V D 8
F 2 5
R S V D 9
F 2 4
R S V D 1 1
D 2 4
R S V D 1 2
G 2 5
R S V D 1 3
G 2 4
R S V D 1 4
E 2 3
R S V D 3 2
W 8
R S V D 3 3
A T 2 6
R S V D 2 5
B 1 8
R S V D 4 4
A P 3 5
R S V D 1 0
F 2 3
R S V D 5
A J 2 6
V A X G_ V A L _ S E N S E
A J 3 1
V S S A X G_ V A L _ S E N S E
A H 3 1
V C C _V A L_ S E N S E
A J 3 3
V S S _ V A L _S E N S E
A H 3 3
K E Y
B 1
V C C _ D I E _ S E N S E
A H 27
V C C I O_ S E L
A 1 9
R S V D 5 4
A N 35
R S V D 5 5
A M 35
C F G 6
C F G 5
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
C FG [6: 5]
R 92 *1 K _ 0 4
PCIE Port Bifurcation Straps
R 99 *1 K _ 0 4
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
C FG 7
R 93 *1 K _ 0 4 C F G 7
3. 3 V 2 , 3 , 11 , 1 3 , 1 5, 1 7 , 1 9, 20 , 2 2 , 23 , 2 7 , 2 9, 3 1 , 3 2, 3 4 , 3 6
1 0/2 9
C F G 2
C FG 2
C F G 4
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
C FG 4
R 11 0 *1 K _ 0 4
R 11 1 *1 K _ 0 4
H _ C P U _R S V D 1
H _ C P U _R S V D 4
H _ C P U _R S V D 3
H _ C P U _R S V D 2
1 0/ 29
C F G 7
C F G 4
C F G 2
C F G 6
C F G 0
C F G 5
1 0/ 29
1. 5 V 3 , 6 , 9 , 1 0, 2 0 , 2 7, 3 2 , 3 4
Sandy Bridge Processor 7/7
( RESERVED )
V R E F _ C H _ A _ D I MM
V R E F _ C H _ B _ D I MM
R 3 9 1 * 10 m i l_ 0 4
3 . 3 V
R 3 9 2 10 K _ 0 4
H _ S N B _ I V B # _P W R C TR L
Sheet 8 of 46
PROCESSOR/
RESERVED