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Schematic Diagrams
B - 4 PROCESSOR/ CLK, MISC, JTAG
B.Schematic Diagrams
PROCESSOR/ CLK, MISC, JTAG
H _ P R O C H OT #
37
S
D
G
Q3 6 B
MT D N 7 00 2 Z H S 6 R
5
3
4
R 9 1
1 0 0 K _0 4
C
LOC
KS
MI
S
C
TH
E
RM
AL
PWR
MA
NA
GEM
EN
T
D
DR3
M
ISC
JT
AG & BP
M
U 3 4B
P Z 9 8 82 7 -3 64 B -0 1 F
S M_ R C OM P [ 1 ]
A 5
S M_ R C OM P [ 2 ]
A 4
S M_ D R A M R S T #
R 8
S M_ R C OM P [ 0 ]
A K 1
B C L K #
A 2 7
B C L K
A 2 8
D P LL _ R E F _S S C L K #
A 1 5
D P L L _ R E F _ S S C L K
A 1 6
C A TE R R #
A L3 3
P E C I
A N 3 3
P R OC H OT #
A L3 2
T H E R MT R I P #
A N 3 2
S M _D R A M P W R OK
V 8
R E S E T #
A R 3 3
P R D Y #
A P 2 9
P R E Q #
A P 2 7
T C K
A R 2 6
T M S
A R 2 7
T R S T #
A P 3 0
T D I
A R 2 8
T D O
A P 2 6
D B R #
A L 35
B P M# [ 0 ]
A T 28
B P M# [ 1 ]
A R 2 9
B P M# [ 2 ]
A R 3 0
B P M# [ 3 ]
A T 30
B P M# [ 4 ]
A P 3 2
B P M# [ 5 ]
A R 3 1
B P M# [ 6 ]
A T 31
B P M# [ 7 ]
A R 3 2
P M _S Y N C
A M3 4
S K T OC C #
A N 3 4
P R OC _S E L E C T #
C 2 6
U N C O R E P W R G OO D
A P 3 3
R 5 9
0 _ 0 4
S3 circuit:- DRAM PWR GOOD logic
1 . 8 V S _ P W R G D
1 5, 3 4
P M_ D R A M_ P W R GD
1 5
P M S Y S _P W R GD _ B U F
R 7 3
* 2 00 _ 1 %_ 0 4
1 . 5V S _C P U
R 5 7
1 0 K _0 4
R 58
* 39 _ 0 4
S U S B
3 2, 3 4 , 3 5
Q 1 0
*M T N 7 0 02 Z H S 3
G
D
S
3 . 3V
11/03
S
D
G
Q3 6 A
MT D N 7 00 2 Z H S 6 R
2
6
1
R 5 3 0
10 K _ 0 4
11/0 4
C 5 15
47p_
50V
_N
P
O
_0
4
H _P R OC H O T#
R 9 0
*0 _ 04
R 6 0
1 30 _ 1 %_ 0 4
CAD Note: Capacitor need to be placed
close to buffer output pin
H _ P R O C H OT _ E C
2 8
Q 1 4
M T N 7 00 2 Z H S 3
G
D
S
C
A
A
D 2 0
*B A T 5 4 A W GH
1
2
3
P MS Y S _ P W R GD _ B U F
R 4 1 4
5 1 _ 04
R 4 1 6
5 1 _ 04
R 1 0 8
5 1 _ 04
R 4 1 5
5 1 _ 04
R 1 0 9
*5 1 _ 04
R 9 5
5 1 _ 04
3. 3V S
1. 0 5 V S _ V T T
XD P _ D B R _ R
R 40 7
1 K _ 0 4
X D P _T M S
X D P _T D O_ R
PU/PD for JTAG signals
X D P _T R S T #
X D P _P R E Q #
X D P _T D I _R
X D P _T C LK
H _ C P U P W R G D _ R
R 1 0 6
* 75 0 _ 1% _ 0 4
R 1 1 2
*1 . 5 K _1 % _ 04
Processor Pullups/Pull downs
TR AC E WI DTH 1 0M IL , LEN GT H <5 00 MIL S
3 . 3V S
B U F _C P U _ R S T#
DDR3 Compensation Signals
S M _R C O MP _ 2
S M _R C O MP _ 1
S M _R C O MP _ 0
C 9 6
*68p
_50V
_N
P
O
_04
V D D P W R GOO D _ R
X D P _ T R S T #
X D P _ T C L K
P L T _ R S T #
1 7 , 23
X D P _ T MS
X D P _ T D I _ R
C P U D R A M R S T #
H _ P R O C H OT # _D
H _ C A TE R R #
Buffered reset to CPU
X D P _ T D O _ R
X D P _ P R E Q#
H _ T H R MT R I P #
1 8
H _ S N B _ I V B #
1 8
R 3 8 2
25 . 5 _ 1% _ 0 4
R 3 8 1
20 0 _ 1% _ 0 4
R 41 9
* 10 m i l_ 0 4
R 4 1 2
1 0 K _ 0 4
R 4 1 3
14 0 _ 1% _ 0 4
H _P E C I
18 , 2 8
P M_ S Y N C _ R
If P ROC HO T# i s n ot u se d, th en i t mu st
be t erm in at ed wi th a 6 8- O + -5 % pu ll -up
re si sto r to 1 .05 VS _V TT .
Sandy Bridge Processor 2/7
( CLK,MISC,JTAG )
R 41 8
* 10 m i l_ 0 4
R 4 1 0
6 2 _ 04
1. 0 5 V S _ V T T
H _P R OC H O T#
S M_ R C OM P _ 2
S M_ R C OM P _ 0
S M_ R C OM P _ 1
C L K _ D P _ N
14
C L K _ E X P _N
1 4
C L K _ E X P _P
14
H _ P M_ S Y N C
15
C L K _ D P _ P 1 4
H _ S N B _ I V B #
1 . 5V
6, 8 , 9 , 1 0 , 20 , 2 7 , 3 2, 3 4
1 . 5V S _C P U
6, 3 2
1 . 05 V S _ V T T
2 , 5 , 1 8 , 19 , 2 0 , 3 5, 3 7
3 . 3V
2, 8 , 1 1 , 13 , 1 5 , 1 7, 1 9 , 2 0, 2 2 , 2 3, 27 , 2 9 , 31 , 3 2 , 3 4, 3 6
H _C P U P W R G D
18
Q8
MT N 70 0 2 Z H S 3
G
D
S
R 4 6
4.
99K
_1%
_04
C P U D R A M R S T #
C 2 2
0 . 0 47 u _ 10 V _ X 7R _ 04
R 4 7
*0 _ 0 4
1 . 5V
R 4 5
1K _ 0 4
S3 circuit:- DRAM_RST# to memory
should be high during S3
D R A MR S T _C N T R L 8 , 1 4
D D R 3 _ D R A MR S T # 9 , 1 0
R 4 8
1 K _ 0 4
10/1
X D P _ D B R _ R
R 41 1
* 10 m i l_ 0 4
X D P _ B P M 1 _R
X D P _ B P M 0 _R
X D P _ B P M 6 _R
X D P _ B P M 5 _R
X D P _ B P M 4 _R
X D P _ B P M 3 _R
X D P _ B P M 2 _R
X D P _ B P M 7 _R
H _ P E C I _ R
R 1 0 5
7 5 _1 % _ 0 4
R 40 5
5 6_ 1 % _0 4
1230 D02
H _ C P U P W R GD _ R
R 1 0 4
43 _ 1 % _0 4
1 0/ 29
R 5 3 1
100
K
_0
4
C 5 85
*0 . 1 u _1 0 V _ X 7R _0 4
X D P _ P R D Y #
1 . 0 5 V S _ V TT
3 . 3V S
9 , 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 18 , 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 28 , 2 9 , 30 , 3 1 , 3 2, 3 7
R 41 7
* 10 m i l_ 0 4
H _ TH R M T R I P # _ R
Sheet 3 of 46
PROCESSOR/ CLK,
MISC, JTAG
Содержание W243HVQ Series
Страница 1: ...W243HVQ Series ...
Страница 2: ......
Страница 3: ...Preface I Preface Notebook Computer W243HVQ Service Manual ...
Страница 24: ...Introduction 1 12 1 Introduction ...
Страница 47: ...Top A 3 A Part Lists Top 灰色 黑色 Figure A 1 Top ...
Страница 48: ...A 4 Bottom with 3G A Part Lists Bottom with 3G Figure A 2 Bottom with SIM W240HUQ W241HUQ W245HUQ Series ...
Страница 49: ...Bottom without 3G A 5 A Part Lists Bottom without 3G Figure A 3 Bottom without 3G ...
Страница 50: ...A 6 SATA BLU RAY COMBO A Part Lists SATA BLU RAY COMBO Figure 4 SATA BLU RAY COMBO ...
Страница 51: ...SATA DVD SUPER MULTI A 7 A Part Lists SATA DVD SUPER MULTI Figure 5 SATA DVD SUPER MULTI ...
Страница 52: ...A 8 A Part Lists LCD 銘板 銅箔接地 Figure A 6 LCD ...
Страница 53: ...HDD A 9 A Part Lists HDD 無鉛 無鉛 Figure A 7 HDD ...
Страница 54: ...A 10 A Part Lists ...
Страница 102: ...Schematic Diagrams B 48 B Schematic Diagrams ...
Страница 105: ...www s manuals com ...