Cisco C880 M5, Руководство по настройке

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Cisco C880 M5 Configuration Guide
21
2.3 Supported IPMI OEM Commands
Response Data - BC
- F1
1 Completion Code:
01 = Unpopulated CPU Socket
2:4 80 28 00 IANA-Enterprise-Number FTS, LS Byte first
5:6 CPU ID, LS Byte first
7 Platform ID
8 Brand ID
9:10 Maximal Core Speed of the CPU [MHz], LS Byte first
11:12 Intel Ultra path Interconnect in Mega Transactions per
second, LS Byte first
13 T-Control Offset
14 T-Diode Offset
15 CPU TJ max
16:17 Record ID CPU Info SDR, LS Byte first
18:19 Record ID Fan Control SDR, LS Byte first
20:21 CPU ID High Word, LS Byte first (optional) (N/A = 0000h)
22:23 Thermal Design Power TDP value with 1/8W granularity,
LS Byte first (optional) (N/A = FFFFh)
24:25 Cache Size (L1) (sum of all L1 caches of socket) Unit
[KB] if MSBit = 0, [MB] if MSBit = 1, LS Byte first (N/A =
FFFFh)
26:27 Cache Size (L2) (sum of all L2 caches of socket) Unit
[KB] if MSBit = 0, [MB] if MSBit = 1, LS Byte first (N/A =
FFFFh)
28:29 Cache Size (L3) (sum of all L3 caches of socket) Unit
[KB] if MSBit = 0, [MB] if MSBit = 1, LS Byte first (N/A =
FFFFh)
30 Maximal Corecount (N/A = FFh)
31 Current Corecount (N/A = FFh)
32 Maximal Threads per Core (N/A = FFh)
33 Current Threads per Core (N/A = FFh)
34:35 CPU Family from SMBIOS (structure 4, offset 6)
36 CPU Manufacturer: 0 = unknown, 1 = INTEL, 2 = AMD