Cirrus Logic CS5460A, Руководство пользователя

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CS5460A
DS284PP4 55
5.2 Current Channel DC Offset Register and Voltage Channel DC Offset Register
Address: 1 (Current Channel DC Offset Register)
3 (Voltage Channel DC Offset Register)
Default** = 0.000
The DC offset registers are initialized to zero on reset, allowing the device to function and perform measure-
ments. The register is loaded after one computation cycle with the current or voltage offset when the proper input
is applied and the DC Calibration Command is received. DRDY will be asserted at the end of the calibration.
The register may be read and stored so the register may be restored with the desired system offset compensa-
tion. The value is in the range ± full scale. The numeric format of this register is two’s complement notation.
5.3 Current Channel Gain Register and Voltage Channel Gain Register
Address: 2 (Current Channel Gain Register)
4 (Voltage Channel Gain Register)
Default** = 1.000
The gain registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The
gain registers hold the result of either the AC or DC gain calibrations, whichever was most recently performed.
If DC calibration is performed, the register is loaded after one computation cycle with the system gain when the
proper DC input is applied and the Calibration Command is received. If AC calibration is performed, then after
~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register) the register(s) is loaded
with the system gain when the proper AC input is applied and the Calibration Command is received. DRDY will
be asserted at the end of the calibration. The register may be read and stored so the register may be restored
with the desired system offset compensation. The value is in the range 0.0
≤
Gain < 4.0.
5.4 Cycle Count Register
Address: 5
Default** = 4000
The Cycle Count Register value (denoted as ‘N’) specifies the number of A/D conversion cycles per computation
cycle. For each computation cycle, the updated results in the RMS and Energy Registers are computed using
the most recent set of N continuous instantaneous voltage/current samples. When the device is commanded
to operate in ’continuous computation cycles’ data acquisition mode, the computation cycle frequency is
(MCLK/K)/(1024
∗
N) where MCLK is master clock input frequency (into XIN/XOUT pins), K is the clock divider
value (as specified in the Configuration Register), and N is Cycle Count Register value.
MSB LSB
-(2
0
) 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB LSB
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
.....
2
-16
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
MSB LSB
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
.....
2
6
2
5
2
4
2
3
2
2
2
1
2
0