Cirrus Logic CS5460A, Руководство пользователя

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CS5460A
12 DS284PP4
2. GENERAL DESCRIPTION
The CS5460A is a CMOS monolithic power mea-
surement device with a real power/energy compu-
tation engine. The CS5460A combines two
programmable gain amplifiers, two
∆Σ
modulators,
two high rate filters, system calibration, and
rms/power calculation functions to provide instan-
taneous voltage/current/power data samples as well
as periodic computation results for real (billable)
energy, V
RMS
, and I
RMS
. In order to accommodate
lower cost metering applications, the CS5460A can
also generate pulse-train signals on certain output
pins, for which the number of pulses emitted on the
pins is proportional to the quantity of real (billable)
energy registered by the device.
The CS5460A is optimized for power measurement
applications and is designed to interface to a shunt
or current transformer to measure current, and a re-
sistive divider or potential transformer to measure
voltage. To accommodate various input voltage
levels, the current channel includes a programma-
ble gain amplifier (PGA) which provides either
±
250 mV or
±
50 mV as the full-scale input level.
The voltage channel’s PGA provides a single input
voltage range of
±
250 mV. With 5 V sup-
ply across VA+/VA- the pins, the differential input
pins of both input channels accommodate common
mode + signal levels between -0.25 V and +5V.
Note that the designer can realize true differential
bipolar input configurations on either/both chan-
nels, in which the common-mode level of the input
signal is at AGND potential (if desired).
The CS5460A includes two high-rate digital filters
(one per channel), which decimate/integrate the out-
put from the 2
∆Σ
modulators. The filters yield
24-bit output data at a (MCLK/K)/1024 output word
rate (OWR). The OWR can be thought of as the ef-
fective sample frequency of the voltage channel and
the current channel.
To facilitate communication to a microcontroller,
the CS5460A includes a simple three-wire serial
interface which is SPI™ and Microwire™ compat-
ible. The serial port has a Schmitt Trigger input on
its SCLK (serial clock) and RESET pins to allow
for slow rise time signals.
2.1 Theory of Operation
A computational flow diagram for the two data
paths is shown in Fig. 3. The reader should refer to
this diagram while reading the following data pro-
cessing
description, which is covered
block-by-block.
2.1.1
∆Σ
Modulators
The analog waveforms at the voltage/current chan-
nel inputs are subject to the gains of the input PGAs
(not shown in Figure 3). These waveforms are then
sampled by the delta-sigma modulators at a rate of
(MCLK/K)/8 Sps.
2.1.2 High-Rate Digital Low-Pass Filters
The data is then low-pass filtered, to remove
high-frequency noise from the modulator output.
Referring to Figure 3, the high rate filter on the
voltage channel is implemented as a fixed Sinc
2
fil-
ter. The current channel uses a Sinc
4
filter, which
allows the current channel to make accurate mea-
surements over a wider span of the total input
range, in comparison to the accuracy range of the
voltage channel. (This subject is discussed more in
Section 2.2.1)
Also note from Figure 3 that the digital data on the
voltage channel is subjected to a variable time-de-
lay filter. The amount of delay depends on the val-
ue of the seven phase compensation bits (see Phase
Compensation), which can be set by the user. Note
that when the phase compensation bits PC[6:0] are
set to their default setting of “0000000” (and if
MCLK/K = 4.096MHz) then the nominal time de-
lay that is imposed on the original analog voltage
input signal, with respect to the original analog cur-
rent input signal, is ~1.0
µ
s. This translates into a
delay of ~0.0216 degrees at 60Hz.