Cirrus Logic CS5460A, Руководство пользователя

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CS5460A
DS284PP4 15
The V
RMS
, I
RMS
, and energy calculations are up-
dated every N conversions (which is known as 1
“computation cycle”), where N is the value in the
Cycle Count Register. At the end of each computa-
tion cycle, the DRDY bit in the Mask Register will
be set, and the INT pin will become active if the
DRDY bit is unmasked.
DRDY is set only after each computation cycle has
completed, whereas the CRDY bit is asserted after
each individual A/D conversion. After any time
that these bits are asserted by the CS5460A, they
must be cleared (by the user) before they can be as-
serted again, so that they can trigger another inter-
rupt event on the INT pin. If the Cycle Count
Register value (N) is set to 1, all output calculations
are instantaneous, and DRDY will indicate when
instantaneous calculations are finished, just like the
CRDY bit. For the RMS results to be valid, the Cy-
cle-Count Register must be set to a value greater
than 10.
The computation cycle frequency is derived from
the
master clock, and has a value of
(MCLK/K)/(1024*N). Under default conditions,
with a 4.096 Mhz clock at XIN, and K = 1, instan-
taneous A/D conversions for voltage, current, and
power are performed at a 4000 Sps rate, whereas
I
RMS
, V
RMS
, and energy calculations are per-
formed at a 1 Sps rate.
2.2.1 CS5460A Linearity Performance
Table 2 lists the range of input levels (as a percent-
age of full-scale registration in the Energy, Irms,
and Vrms Registers) over which the (lin
variation) of the results in the Vrms, Irms and En-
ergy Registers are guaranteed to be within
±
0.1% of
reading, after the completion of each successive
computation cycle. Note that until the CS5460A is
calibrated (see Calibration) the accuracy of the
CS5460A (with respect to a reference line-voltage
and line-current level on the power mains) is not
guaranteed to within
±
0.1%. But the linearity of
any given sample of CS5460A, before calibration,
will indeed be to within ±0.1% of reading over the
ranges specified, with respect to the input voltage
levels required (on the voltage and current chan-
nels) to cause full-scale readings in the Irms/Vrms
Registers. After both channels of the device are
calibrated for offset/gain, the ±0.1% of reading
spec will also reflect accuracy of the Vrms, Irms,
and Energy Register results. Finally, observe that
the typical maximum (full-scale) differential input
voltage for the voltage channel (and current chan-
nel, when its PGA is set for 10x gain) is 250mV
(nominal). If the gain registers of both channels
are set to 1 (default) and the two DC offset reg-
isters are set to zero (default), then a 250mV dc
signal applied to the voltage/current inputs will
measure at (or near) the maximum value of
0.9999... in the RMS Current/Voltage Registers.
Remember that the RMS value of a 250mV (dc)
signal is also 250mV. However, for either input
channel, it would not be practical to inject a sinuso-
idal voltage with RMS value of 250mV. This is be-
cause when the instantaneous value of such a sine
Input Voltage (DC)
Output Code
(hexidecimal)
Output Code
(decimal)
+250mV 7FFFFF 8388607
14.9nV to 44.7nV 000001 1
-14.9nV to 14.9nV 000000 0
-44.7nV to -14.9nV FFFFFF -1
-250mV 800000 -8388608
Table 1. Differential Input Voltage vs. Output Code
Energy Vrms Irms
Range (% of FS)
0.1% - 100%
50% - 100% 0.2% - 100%
Max. Differential
Input
not applicable
V-channel:
±250mV
I-channel:
±250mV 10x
±50mV
50x
Linearity 0.1% of
reading 0.1% of
reading 0.1% of
reading
Table 2. Available range of ±0.1% output linearity, with
default settings in the gain/offset registers.