Cirrus Logic CS5460A, Руководство пользователя

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CS5460A
16 DS284PP4
wave is at or near the level of its positive/negative
peak regions (over each cycle), the voltage level of
this signal would exceed the maximum differential
input voltage range of the input channels. The larg-
est sine wave voltage signal that can be presented
across the inputs, with no saturation of the inputs,
is (typically) 250mV / sqrt(2) = ~176.78 mV
(RMS), which is at ~70.7% of full-scale.
This
would imply that for the current channel, the (lin-
variation) tolerance of the RMS measure-
ments for a purely sinusoidal 60 Hz input signal
could be measured to within
±
0.1% of reading over
a magnitude range of 0.2% - 70.7% (of the maxi-
mum full-scale differential input voltage level).
The range over which the (lin variation)
will remain within ±0.1% of reading can often be
increased by selecting a value for the Cycle-Count
Register such that the time duration of one compu-
tation cycle is equal to (or very close to) a
whole-number of power-line cycles (and N must be
greater than or equal to 4000). For example, with
the cycle count set to 4200, the ±0.1% of reading
(lin variation) range for measurement of a
60 Hz sinusoidal current-sense voltage signal (cre-
ated by sensing the current on a power line) can be
increased beyond the range of 0.2% - 70.7%. The
accuracy range will be increased because (4200
samples / 60 Hz) is a whole number of cycles (70).
Note that this increase in the measurement range
refers to an extension of the low end of the input
scale (i.e., this does not extend the high-end of the
range above 100% of full-scale). This enables ac-
curate measurement of even smaller power-line
current levels, thereby extending the load range
over which the power meter can make accurate en-
ergy measurements. Increasing the accuracy range
can be beneficial for power metering applications
which require accurate power metering over a very
large load range.
2.2.2 Single Computation Cycle (C=0)
Note that ‘C’ refers to the value of the C bit, con-
tained in the ‘Start Conversions’ command (see
Section 3.1).
This commands instructs the
CS5460A to perform conversions in ‘single com-
putation cycle’ data acquisition mode. Based on
the value in the Cycle Count Register, a single
computation cycle is performed after the user trans-
mits the ‘Start Conversions’ command to the serial
interface. After the computations are complete,
DRDY is set. 32 SCLKs are then needed to read out
a calculation result from one of several result regis-
ters. The first 8 SCLKs are used to clock in the
command to determine which register is to be read.
The last 24 SCLKs are used to read the desired reg-
ister. After reading the data, the serial port remains
in the active state, and waits for a new command to
be issued. (See Section 3 for more details on read-
ing register data from the CS5460A).
2.2.3 Continuous Computation Cycles (C=1)
When C=1, the CS5460A will perform conversions
in ‘continuous computation cycles’ data acquisition
mode. Based on the information provided in the Cy-
cle Count Register, computation cycles are repeat-
edly performed on the voltage and current channels
(after every N conversions). Computation cycles
cannot be started/stopped on a ‘per-channel’ basis.
After each computation cycle is completed, DRDY
is set. Thirty-two SCLKs are then needed to read a
register. The first 8 SCLKs are used to clock in the
command to determine which results register is to be
read. The last 24 SCLKs are used to read out the
24-bit calculation result. While in this acquisition
mode, the designer/programmer may choose to ac-
quire (read) only those calculations required for
their particular application, as DRDY repeatedly in-
dicates the availability of new data. Note again that
the user’s MCU firmware must reset the DRDY bit
to “0” before it can be asserted again.
Referring again to Figure 3, note that within the
Irms and Vrms data paths, prior to the square-root