CHAPTER 2. BASIC OPERATION
2–7
C. Image Controller
Figure 2-104 is a block diagram of the image controller.
Figure 2-104
Address bus
32-bit data bus
[12]
CPU
(U607)
Y601
14.7MHz
Y602
33MHz
Engine controller
[9]
FLASH
ROM
(U612,
U618)
[8]
FLASH
ROM
(XU601)
[4]
SRAM
(U628)
[3]
DRAM
(U602,606,
U611,U616)
[2]
FIFO
(U622)
[1]
Serial
controller
(U632)
[7]
Gate array
(U617)
[10]
EEPROM
(U619)
Operation
Panel
[11]
PIO
(U629,
U634)
8-bit
Data bus
Address bus
32-bit
Data bus
Address bus
[13]
Reset IC
(U613)
Image controller
External serial
interface
16-bit
data bus
32-bit
data bus
8-bit
8-bit
data bus
Y601
14.7MHz
External parallel interface
[6]
Serial
controller
(U633)
Communication
I/F
[5]
Timer
(U610)
[14]
Timer
(U609)
Image data I/F(8-bit)
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