K11208a;31/36
- 31 -
8. Timing Chart
●
Pixel clock timing (common in various operation modes)
[Phase relationship between clock output and data]
(Note) The above timing represents the signal timing before being encoded to serial data by the channel link device on the
side of the sending end (the part circled in the above right figure). If signal conversion from serial to parallel is made by
a channel link device in accordance with the Camera Link standard on the side of the receiving end, the phase
relationship between the clock and the data after decoding will be different from that of the above timing due to the
structural nature of a channel link device. (In the case of the output from a channel link device, the data are aligned
with the trailing edge of the clock signal.) As a general rule, this variation in timing is correctly adjusted at the capture
timing of a capture board, the equal definition file to that of the conventional parallel output type can be used for
capturing.
(!) 8 or 10 bit x 2 tap output is employed for FC1600FCL. Therefore, there is no compatibility with the conventional parallel
type camera FC2000CL etc. and so dedicated setting files are required.
(Note) When a channel link device is mounted directly to the capture interface on the user side, instead of using a
commercially available capture board that supports Camera Link, it is necessary to pay close attention to the
descriptions of the data sheet of the channel link device including the phase relationship between data and clock prior to
the use.
●
Horizontal timing
ＨＤ
１ ６８
１hor izo nta l t ime （ １ Ｈ）
（
Internal horizontal
synch signal
）
１ ８ ７ ４
Digital output
（ＣＨ１，２）
Eff ect ive ima ge dur atio n
１３ ９ ０
ＬＤＶ
CCD output signal
Ho rizo nta l t ran sfer
su spen sio n t ime
OB
2 0
４ １ ７
2
Effe cti ve pix els
１ ３ ９２
３ ８
４０ １
１ ２
４
３
５
１
３
８
８
１
３
８
９
１
３
９
１
１
３
９
０
１
３
９
２
Ｏ Ｂ
４ ０
ＣＬＫ
１ Ｃ
（ ２）
11
12
3
4
13 91
13 92
138 9
139 0
138 7
138 8
138 5
138 6
1 383
1 384
5
6
7
8
9
1 0
１
７ ６Ｃ
１ ７０ Ｃ
Ｏ Ｂ
４ ０
D M
４０ Ｃ
３ ８
ＦＤＶ
１ ７Ｃ
* Unless otherwise specified, the time unit of the numbers in the horizontal timing chart is pixel CLK (= 1/60.0MHz = 16.7nS).
* The numbers shown here are design values, and the actual equipment should be checked for the details.
CH2:10bit
CH1: 10bit
10ns (max)
CLK
Clock output
1CLK=33.3nS
Digital data
DEMULTIPLEX.
A/D
10bit
CH1
(LDV, FDV)
PCLK
1/2
10/8bit
CLK
CH2
10/8bit
C
h
a
n
n
e
l
L
in
k
C
a
m
e
ra
L
in
k
B
a
s
e
C
o
n
fi
g
u
ra
ti
o
n
Camera Link
connector
