
Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V2718 VME PCI Optical Link Bridge
03/07/2018
11
NPO:
Filename:
Number of pages:
Page:
00106/03:V2718.MUTx/11
V2718_REV11.DOC
79
3
TABLE OF CONTENTS
1.
GENERAL DESCRIPTION ........................................................................................................................... 8
1.1.
O
VERVIEW
............................................................................................................................................... 8
1.2.
B
LOCK DIAGRAM
.................................................................................................................................... 10
1.3.
CONET
L
AYOUT
................................................................................................................................... 11
2.
VME INTERFACE ....................................................................................................................................... 12
2.1.
VME
BUS
R
EQUESTER
........................................................................................................................... 12
2.1.1.
Fair and Demand Request modes .................................................................................................. 13
2.1.2.
VME bus Release .......................................................................................................................... 13
2.2.
A
DDRESSING CAPABILITIES
.................................................................................................................... 13
2.3.
D
ATA TRANSFER CAPABILITIES
.............................................................................................................. 14
2.4.
I
NTERRUPT CAPABILITIES
....................................................................................................................... 14
2.5.
C
YCLE TERMINATIONS
........................................................................................................................... 15
2.6.
S
LAVE
.................................................................................................................................................... 16
2.7.
L
OCATION
M
ONITOR
.............................................................................................................................. 17
2.8.
VME
BUS
F
IRST
S
LOT
D
ETECTOR
.......................................................................................................... 17
2.9.
S
YSTEM
C
ONTROLLER
F
UNCTIONS
......................................................................................................... 18
2.9.1.
System Clock Driver ..................................................................................................................... 18
2.9.2.
Arbitration Module ........................................................................................................................ 18
2.9.2.1.
Fixed Priority Arbitration Mode (PRI) ................................................................................ 18
2.9.2.2.
Round Robin Arbitration Mode (RRS) ................................................................................. 18
2.10.
B
US
T
IMER
............................................................................................................................................. 18
2.11.
IACK
D
AISY
C
HAIN
D
RIVER
.................................................................................................................. 19
2.12.
VME64X
C
YCLES NOT YET IMPLEMENTED
............................................................................................ 19
2.13.
I
NTERNAL REGISTERS
............................................................................................................................. 20
2.13.1.
Status register ................................................................................................................................ 21
2.13.2.
Control register .............................................................................................................................. 22
2.13.3.
Firmware Revision register............................................................................................................ 22
2.13.4.
Firmware Download register ......................................................................................................... 23
2.13.5.
Flash Enable register ..................................................................................................................... 23
2.13.6.
IRQ Status register......................................................................................................................... 23
2.13.7.
IRQ Mask register ......................................................................................................................... 23
2.13.8.
Input register .................................................................................................................................. 24
2.13.9.
Output set register .......................................................................................................................... 24
2.13.10.
Output clear register ...................................................................................................................... 25
2.13.11.
Input Multiplexer Set register ........................................................................................................ 26
2.13.12.
Input Multiplexer Clear register .................................................................................................... 27
2.13.13.
Output Multiplexer Set register ..................................................................................................... 28
2.13.14.
Output Multiplexer Clear register .................................................................................................. 29
2.13.15.
LED Polarity set register ............................................................................................................... 29
2.13.16.
LED polarity clear register ............................................................................................................ 30
2.13.17.
Pulser A 0 register ......................................................................................................................... 30
2.13.18.
Pulser A 1 register ......................................................................................................................... 30
2.13.19.
Pulser B 0 register.......................................................................................................................... 31
2.13.20.
Pulser B 1 register.......................................................................................................................... 31
2.13.21.
Scaler 0 register ............................................................................................................................. 31
2.13.22.
Scaler 1 register ............................................................................................................................. 32
2.13.23.
Display Address Low register ....................................................................................................... 32
2.13.24.
Display Address High register ....................................................................................................... 32
2.13.25.
Display Data Low register ............................................................................................................. 32