
Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V2718 VME PCI Optical Link Bridge
03/07/2018
11
NPO:
Filename:
Number of pages:
Page:
00106/03:V2718.MUTx/11
V2718_REV11.DOC
79
16
VME BUS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
AM0
AM1
AM2
AM3
AM4
AM5
IRQ1
IRQ2
IRQ3
IRQ7
BRQ
IRQ4
IRQ5
IRQ6
DT K
BERR
BGR
SRES
LWRD
DS0
DS1
AS
IACK
WR
D
IS
P
_
A
D
D
IS
P
_
D
T
D
IS
P
_
C
TR
L
32
32
24
RAM
32 x 16
32
2.6. Slave
The V2718 can be operated as slave for debugging purposes. It responds to VME cycles
(which must be initiated by another master, i.e. a V2718 cannot
address itself
as a slave)
for accessing the Dataway Display internal registers and a Test RAM (32 x 16). The
V2718 is accessed both with A32 and A24 base address (see §
); the module is
provided with only two rotary switches for board addressing, so the addressing mode is
selected via the dip switch 3 (A24
→
PROG_3 = OFF; A32
→
PROG_3 = ON), see §
The Address map for V2718 is listed in Table 2.1. All register addresses are referred to
the Base Address of the board, i.e. the addresses reported in the Tables are the offsets
to be added to the board Base Address.
Table 2.1: Address Map for the Model V2718
ADDRESS
REGISTER/CONTENT
ADDR_MODE
DATA_MODE
R/W
Base + %0000
%00FC Test RAM
A24/A32
D32, BLT32, MBLT Read/Write
Base + %1000
Display Address
A24/A32
D32
Read only
Base + %1004
Display Data
A24/A32
D32
Read only
Base + %1008
Display Control
A24/A32
D32
Read only
Fig. 4: V2718 Slave operation