
Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V2718 VME PCI Optical Link Bridge
03/07/2018
11
NPO:
Filename:
Number of pages:
Page:
00106/03:V2718.MUTx/11
V2718_REV11.DOC
79
23
2.13.4.
Firmware Download register
(Base A 0x03, D16, read/write)
This register is reserved for internal use only.
2.13.5.
Flash Enable register
(Base A 0x04, D16, read/write)
This register is reserved for internal use only.
2.13.6.
IRQ Status register
(Base A 0x05, D16, read only)
This register allows to monitor the IRQ lines status (1 = Active, 0 = Inactive).
Fig. 9: IRQ Status register
2.13.7.
IRQ Mask register
(Base A 0x06, D16, read/write)
This register allows to mask the IRQ lines (1 = Masked, 0 = Unmasked). If one line is
masked, the interrupt on the VME bus is not transmitted to the PCI bus.
Fig. 10: IRQ Mask register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7