II-10
<HL-730/730Plus>
The ASIC is composed of Cell Based IC and has the following function blocks.
(1) Oscillator circuit
Generates the main clock for the CPU by dividing the source clock frequency into
two.
(2) Address decoder
Generates the CS for each device.
(3) DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls
refresh recessing (CAS before RAS self-refreshing method).
(4) Interrupt control
Interrupt levels:
Priority High
7
NMI
6
FIFO
5
EXINT(Option Serial I/O)
4
BD / Timer 1
3
SCANINT
2
CDCC / BOISE / DATA EXTENTION
Low
1
Timer 2
(5) Timers
The following timers are incorporated:
Timer 1
16-bit timer
Timer 2
10-bit timer
Timer 3
Watch-dog timer
(6) FIFO
A 5,120-bit FIFO is incorporated. Data for one raster is transferred from the RAM
to the FIFO by DMA transmission and is output as serial video data. The data cycle
is 6.13 MHz.
Содержание HL-720
Страница 1: ...SERVICE MANUAL MODEL HL 720 730 730Plus R LASER PRINTER ...
Страница 36: ...II 19 1 3 10 Engine I O HL 720 Fig 2 21 shows the engine interface circuit Fig 2 21 ...
Страница 37: ...II 20 HL 730 730Plus Fig 2 22 shows the engine interface circuit Fig 2 22 ...
Страница 61: ... Fig 3 18 2 4 1 1 1 ...
Страница 92: ...SERVICE MANUAL MODEL HL 760 R LASER PRINTER ...
Страница 109: ...II 8 1 3 4 DRAM Two 4M bit DRAMs x 16bits are used as the RAM Fig 2 6 ...
Страница 113: ...II 12 1 3 10 Engine I O Fig 2 12 shows the engine interface circuit Fig 2 12 ...
Страница 114: ...II 13 1 3 11 Paper Feed Motor Drive Circuit Fig 2 13 ...
Страница 133: ...Appendix 2 Main PCB Circuit Diagram 1 3 CODE UK3227000 B48K272CIR 1 3 NAME ...
Страница 134: ...Appendix 3 Main PCB Circuit Diagram 2 3 CODE UK3227000 B48K272CIR 2 3 NAME ...
Страница 135: ...CODE UK3227000 B48K272CIR 3 3 NAME Appendix 4 Main PCB Circuit Diagram 3 3 ...
