Beckhoff KL31 2 Series, Документация

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Product overview
KL31x2 14 Version: 2.4.0
Key
Name Name Unit Register
X
ADC
Output value of the A/D converter [1] -
Y
out
Process data for controller [1] -
B
A
Vendor calibration: Offset (can be disabled via bit R32.5 [ } 49] of the
feature register)
[1]
R17 [ } 47]
A
A
Vendor calibration: Gain (always active) [1 x 2
-16
+ 1]
R18 [
}
47]
B
K
Calibration: Offset (can be enabled via bit R32.5 [
}
49] of the feature
register)
[1]
R1 [
}
46]
A
K
Calibration: Gain (can be enabled via bit R32.5 [ } 49] of the feature
register)
[1]
R2 [ } 46]
A
GK
Basic calibration: Gain (can be enabled via bit R32.5 [ } 49] of the
feature register)
[1]
R23 [ } 48]
B
H
Manufacturer scaling: Offset (can be enabled via bit R32.1 [
}
49] of the
feature register)
[1]
R19 [
}
48]
A
H
Manufacturer scaling: Gain (can be enabled via bit R32.1 [
}
49] of the
feature register)
[1 x 2
-8
+ 1]
R20 [
}
48]
B
W
User scaling: Offset (can be enabled via bit R32.0 [
}
49] of the feature
register)
[1]
R33 [
}
50]
A
W
User scaling: Gain (can be enabled via bit R32.0 [
}
49] of the feature
register)
[1 x 2
-8
+ 1]
R34 [
}
50]
Calibration
The analog channels are self‑calibrated periodically. Analog switches are provided for this purpose, so that
the various calibration signals can be connected. It is important for this process that the entire signal path,
including all passive components, is examined at every phase of the calibration. Only the interference
suppression elements (L/C combination) and the analog switches themselves cannot be examined.
The calibration interval is set in register R40 [
}
51] in steps of 100 ms. During calibration, no current process
data are present. Value 0 is present. The terminal indicates active calibration by setting bit SB1.6 [
}
42] in
the status byte, and by switching off the associated RUN LED. Calibration can be disabled by the controller
via control byte
CB1.1 [ } 42] if necessary. If calibration is disabled over a prolonged period, the terminal
carries out a forced calibration, in order to compensate any voltage drifts that may be caused by changes in
temperature. The forced calibration interval is specified via register
R44 [ } 51] as a multiple of the calibration
interval. If a further calibration between two cycles is required, this can be started manually by setting bit
CB1.0 [
}
42] . The terminal then acts as if it had triggered a calibration itself.
Fluctuating measurement signals disturbing the self‑calibration
The terminal checks by a stabilization test while in calibration state whether the input signal is sta-
ble. Large variations of measurement signals prevent a completion of the self‑calibration; the termi-
nal remains in Error=1 and overload/underload=1, see sections
"Basic function principles/ Calibra-
tion" [ } 14] and "Access from the user program/ Status byte 1 (for process data mode)" [ } 42] .
If such a signal will be expected on a system plant, you can optionally:
‑ lock the self‑calibration within the process via Control‑Bit
CB 1.1 [
}
42] as long a smooth signal is
present and the self‑calibration passes.
‑ disabling the stabilization test process via bit
R32.7 [
}
48] .
‑ disabling the indication of the stabilization error by bit R32.14 [
}
48] .
‑ increase the tolerance window of the stabilization control by register R48 [
}
51] .
The functionality of the calibration including all features invariably refers to both channels simultaneously!
The channels cannot be calibrated individually. For this reason, the registers
R40 [
}
51] , R44 [
}
51] , R47
[
}
51] and R48 [
}
51] are only implemented once for both channels.