Product overview
EP1518-0002
14
Version: 2.4
3.4
Process image
The process image depends on the selected
Operation mode: 2 counters and 2 digital inputs (delivery state)
The input data of the 1st counter can be found under
CNT
Input Channel 1
.
The adoption of the
Set counter
bit from
CNT Output
Channel 1
is displayed with
Set counter done.
The adoption of the
Inhibit counter
bit from
CNT Output
Channel 1
is displayed with
Counter inhibited
.
Status of input UD
shows the status of the Up/Down counter
input of the 1st counter.
Status of input clock
shows the status of the input clock input
of the 1st counter.
Sync Error, TxPDO State and TxPDO Toggle are standard
EtherCAT process data.
The input data of the 2nd counter can be found under
CNT
Input Channel
2. Their structure corresponds to that of the 1st
counter.
DIG Inputs
shows the states of the individual inputs
irrespective of the selected operation mode.
Error channel 1
displays a short circuit of the supply voltage
Us to digital inputs 0 to 3.
Error channel 2
displays a short circuit of the supply voltage
Us to digital inputs 4 to 7.
The output data of the 1st counter can be found under
CNT
Output Channel 1
.
The setting of
Set counter
activates the adoption of the
Set
Counter Value
into the
Counter Value
of the 1st counter.
The setting of
Inhibit Counter
disables the 1st counter.
Alternatively the counter can be disabled or enabled by the
physical GATE input.
The two values are XORed.
The output data of the 2nd counter can be found under
CNT
Output Channel 1
. Their structure corresponds to that of the
1st counter.