AXIOMTEK SBC81872, Руководство пользователя

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SBC81872 Socket479 All-in-One CPU Card Series User’s Manual
Award BIOS Setup 49
z
DRAM RAS# to CAS# Delay
This field let’s you insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from, or
refreshed. Fast gives faster performance; and Slow gives more
stable performance. This field applies only when synchronous
DRAM is installed in the system.
The Choice: 3, 2.
z
DRAM RAS# Precharge
If an insufficient number of cycles is allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh may be
incomplete and the DRAM may fail to retain data. Fast gives
faster performance; and Slow gives more stable performance.
This field applies only when synchronous DRAM is installed in
the system.
The Choice: 2, 3.
z
Precharge Delay
This item controls the number of DRAM clocks for TRAS.
The Choice: 7, 6, 5.
z
SLP_S4# Assertion Width
The options are 1 to 2 Sec., 2 to 3 Sec., 3 to 4 Sec. and 4 to 5
Sec
z
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter
ROM. When this area is reserved, it can’t be
Cached. The user information of peripherals that need
to use this area of system memory usually discusses their
memory requirements.
z
PCI Express Root Port Func
Move the cursor to this filed and press <Enter>. The screen will
appear
.